| Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Google Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
| 20 | config NORTHBRIDGE_INTEL_HASWELL |
| 21 | bool |
| 22 | select CACHE_MRC_BIN |
| 23 | select CPU_INTEL_HASWELL |
| 24 | select REQUIRES_BLOB |
| Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 25 | select MMCONF_SUPPORT_DEFAULT |
| Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | |
| 27 | if NORTHBRIDGE_INTEL_HASWELL |
| 28 | |
| Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 29 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 30 | string |
| 31 | default "northbridge/intel/haswell/bootblock.c" |
| 32 | |
| Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 33 | config VGA_BIOS_ID |
| 34 | string |
| 35 | default "8086,0166" |
| 36 | |
| 37 | config EXTERNAL_MRC_BLOB |
| 38 | bool |
| 39 | default n |
| 40 | |
| 41 | config CACHE_MRC_SIZE_KB |
| 42 | int |
| 43 | default 512 |
| 44 | |
| 45 | # FIXME: build from rom size |
| 46 | config MRC_CACHE_BASE |
| 47 | hex |
| 48 | default 0xff800000 |
| 49 | |
| 50 | config MRC_CACHE_LOCATION |
| 51 | hex |
| 52 | depends on !CHROMEOS |
| 53 | default 0x370000 |
| 54 | |
| 55 | config MRC_CACHE_SIZE |
| 56 | hex |
| 57 | depends on !CHROMEOS |
| 58 | default 0x10000 |
| 59 | |
| 60 | config DCACHE_RAM_BASE |
| 61 | hex |
| 62 | default 0xff7e0000 |
| 63 | |
| 64 | config DCACHE_RAM_SIZE |
| 65 | hex |
| 66 | default 0x20000 |
| 67 | |
| 68 | config DCACHE_RAM_MRC_VAR_SIZE |
| 69 | hex |
| 70 | default 0x4000 |
| 71 | |
| 72 | config HAVE_MRC |
| 73 | bool "Add a System Agent binary" |
| 74 | help |
| 75 | Select this option to add a System Agent binary to |
| 76 | the resulting coreboot image. |
| 77 | |
| 78 | Note: Without this binary coreboot will not work |
| 79 | |
| 80 | config MRC_FILE |
| 81 | string "Intel System Agent path and filename" |
| 82 | depends on HAVE_MRC |
| 83 | default "mrc.bin" |
| 84 | help |
| 85 | The path and filename of the file to use as System Agent |
| 86 | binary. |
| 87 | |
| 88 | config CBFS_SIZE |
| 89 | hex "Size of CBFS filesystem in ROM" |
| 90 | default 0x100000 |
| 91 | help |
| 92 | On Haswell systems the firmware image has to store a lot more |
| 93 | than just coreboot, including: |
| 94 | - a firmware descriptor |
| 95 | - Intel Management Engine firmware |
| 96 | - MRC cache information |
| 97 | This option allows to limit the size of the CBFS portion in the |
| 98 | firmware image. |
| 99 | |
| 100 | endif |