Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 1 | config SOC_AMD_COMMON_BLOCK_CAR |
| 2 | bool |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 3 | help |
| 4 | This option allows the SOC to use a standard AMD cache-as-ram (CAR) |
Marshall Dawson | d61e832 | 2017-08-09 19:59:20 -0600 | [diff] [blame] | 5 | implementation. CAR setup is built into bootblock and teardown is |
| 6 | in postcar. The teardown procedure does not preserve the stack so |
| 7 | it may not be appropriate for a romstage implementation without |
| 8 | additional consideration. If this option is not used, the SOC must |
| 9 | implement these functions separately. |
Felix Held | befec1e | 2020-11-06 00:26:03 +0100 | [diff] [blame] | 10 | This is only used for AMD CPU before family 17h. From family 17h on |
| 11 | the RAM is already initialized by the PSP before the x86 cores are |
| 12 | released from reset. |
Felix Held | 9065f4f | 2020-11-21 02:12:54 +0100 | [diff] [blame] | 13 | |
| 14 | config SOC_AMD_COMMON_BLOCK_NONCAR |
| 15 | bool |
Felix Held | 9065f4f | 2020-11-21 02:12:54 +0100 | [diff] [blame] | 16 | help |
| 17 | From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any |
| 18 | more, since the RAM initialization is already done by the PSP when |
| 19 | the x86 cores are released from reset. |
| 20 | |
| 21 | if SOC_AMD_COMMON_BLOCK_NONCAR |
| 22 | |
Arthur Heymans | 4be0f4b | 2022-03-30 23:08:21 +0200 | [diff] [blame] | 23 | config BOOTBLOCK_IN_CBFS |
| 24 | bool |
| 25 | default n |
| 26 | |
Felix Held | 9065f4f | 2020-11-21 02:12:54 +0100 | [diff] [blame] | 27 | config MEMLAYOUT_LD_FILE |
| 28 | string |
| 29 | default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" |
| 30 | |
Raul E Rangel | 55fea11 | 2021-07-23 16:43:18 -0600 | [diff] [blame] | 31 | config CBFS_CACHE_SIZE |
| 32 | hex |
| 33 | help |
| 34 | The size of the cbfs_cache region. |
| 35 | |
Felix Held | 6494265 | 2023-03-04 03:33:54 +0100 | [diff] [blame] | 36 | config ACPI_CPU_STRING |
| 37 | string |
Felix Held | 3cf05b5 | 2023-05-15 19:16:22 +0200 | [diff] [blame^] | 38 | default "C%03X" |
Felix Held | 6494265 | 2023-03-04 03:33:54 +0100 | [diff] [blame] | 39 | |
Felix Held | 9065f4f | 2020-11-21 02:12:54 +0100 | [diff] [blame] | 40 | endif # SOC_AMD_COMMON_BLOCK_NONCAR |
Felix Held | 2f5c759 | 2020-12-04 17:31:10 +0100 | [diff] [blame] | 41 | |
Felix Held | 96fd62f | 2023-03-24 16:55:50 +0100 | [diff] [blame] | 42 | config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H |
| 43 | bool |
| 44 | help |
| 45 | Select this option to include code to calculate the CPU frequency |
| 46 | from the P state MSR values on AMD CPU families 15h and 16h. |
| 47 | |
Felix Held | a63f859 | 2023-03-24 16:30:55 +0100 | [diff] [blame] | 48 | config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H |
| 49 | bool |
| 50 | help |
| 51 | Select this option to include code to calculate the CPU frequency |
| 52 | from the P state MSR values on AMD CPU families 17h and 19h. |
| 53 | |
| 54 | config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH |
| 55 | bool |
| 56 | help |
| 57 | Select this option to include code to calculate the CPU frequency |
| 58 | from the P state MSR values on AMD CPU family 1Ah. |
| 59 | |
Felix Held | 1e1d490 | 2021-07-14 00:05:39 +0200 | [diff] [blame] | 60 | config SOC_AMD_COMMON_BLOCK_MCA_COMMON |
| 61 | bool |
| 62 | help |
| 63 | Add common machine check architecture support. Do not select this |
| 64 | in the SoC's Kconfig; select either SOC_AMD_COMMON_BLOCK_MCA or |
| 65 | SOC_AMD_COMMON_BLOCK_MCAX which will select this one. |
| 66 | |
| 67 | config SOC_AMD_COMMON_BLOCK_MCA |
| 68 | bool |
| 69 | select SOC_AMD_COMMON_BLOCK_MCA_COMMON |
| 70 | help |
| 71 | Add IA32 machine check architecture (MCA) support for pre-Zen CPUs. |
| 72 | |
| 73 | config SOC_AMD_COMMON_BLOCK_MCAX |
| 74 | bool |
| 75 | select SOC_AMD_COMMON_BLOCK_MCA_COMMON |
| 76 | help |
| 77 | Add extended machine check architecture (MCAX) support for AMD family |
| 78 | 17h, 19h and possibly newer CPUs. |
| 79 | |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 80 | config SOC_AMD_COMMON_BLOCK_SMM |
| 81 | bool |
Arthur Heymans | 56776a1 | 2022-05-19 11:31:10 +0200 | [diff] [blame] | 82 | select X86_SMM_SKIP_RELOCATION_HANDLER if HAVE_SMI_HANDLER |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 83 | help |
Felix Held | 746f438 | 2021-02-16 17:42:56 +0100 | [diff] [blame] | 84 | Add common SMM relocation, finalization and handler functionality to |
| 85 | the build. |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 86 | |
Felix Held | 23a398e | 2023-03-23 23:44:03 +0100 | [diff] [blame] | 87 | config SOC_AMD_COMMON_BLOCK_SVI2 |
| 88 | bool |
| 89 | help |
| 90 | Select this option is the SoC uses the serial VID 2 standard for |
| 91 | encoding the voltage it requests from the VRM. |
| 92 | |
| 93 | config SOC_AMD_COMMON_BLOCK_SVI3 |
| 94 | bool |
| 95 | help |
| 96 | Select this option is the SoC uses the serial VID 3 standard for |
| 97 | encoding the voltage it requests from the VRM. |
| 98 | |
Felix Held | 60df7ca | 2023-03-24 20:33:15 +0100 | [diff] [blame] | 99 | config SOC_AMD_COMMON_BLOCK_TSC |
Felix Held | 2f5c759 | 2020-12-04 17:31:10 +0100 | [diff] [blame] | 100 | bool |
Felix Held | 2f5c759 | 2020-12-04 17:31:10 +0100 | [diff] [blame] | 101 | select TSC_SYNC_LFENCE |
| 102 | select UDELAY_TSC |
Felix Held | 26d54b7 | 2023-03-24 20:37:47 +0100 | [diff] [blame] | 103 | select TSC_MONOTONIC_TIMER |
Felix Held | 2f5c759 | 2020-12-04 17:31:10 +0100 | [diff] [blame] | 104 | help |
| 105 | Select this option to add the common functions for getting the TSC |
Felix Held | 60df7ca | 2023-03-24 20:33:15 +0100 | [diff] [blame] | 106 | frequency of AMD family 17h, 19h and 1Ah CPUs/APUs and to provide |
| 107 | TSC-based monotonic timer functionality to the build. |
Raul E Rangel | 394c6b0 | 2021-02-12 14:37:43 -0700 | [diff] [blame] | 108 | |
| 109 | config SOC_AMD_COMMON_BLOCK_UCODE |
| 110 | bool |
Raul E Rangel | 394c6b0 | 2021-02-12 14:37:43 -0700 | [diff] [blame] | 111 | help |
| 112 | Builds in support for loading uCode. |