Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip soc/intel/skylake |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 4 | register "SerialIoDevMode" = "{ |
| 5 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ |
| 6 | }" |
| 7 | |
| 8 | register "eist_enable" = "1" |
| 9 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 10 | device cpu_cluster 0 on end |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 11 | device domain 0 on |
| 12 | subsystemid 0x103c 0x2b5e inherit |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 13 | device ref peg0 on end |
| 14 | device ref igpu on end |
| 15 | device ref sa_thermal on end |
| 16 | device ref gmm on end |
| 17 | device ref south_xhci on |
Felix Singer | e6f1924 | 2023-10-23 17:15:34 +0200 | [diff] [blame] | 18 | register "usb2_ports" = "{ |
| 19 | [0] = USB2_PORT_MID(OC0), |
| 20 | [1] = USB2_PORT_MID(OC0), |
| 21 | [2] = USB2_PORT_MID(OC4), |
| 22 | [3] = USB2_PORT_MID(OC4), |
| 23 | [4] = USB2_PORT_MID(OC2), |
| 24 | [5] = USB2_PORT_MID(OC2), |
| 25 | [6] = USB2_PORT_MID(OC0), |
| 26 | [7] = USB2_PORT_MID(OC0), |
| 27 | [8] = USB2_PORT_MID(OC0), |
| 28 | [9] = USB2_PORT_MID(OC0), |
| 29 | [10] = USB2_PORT_MID(OC1), |
| 30 | [11] = USB2_PORT_MID(OC1), |
| 31 | [12] = USB2_PORT_MID(OC_SKIP), |
| 32 | [13] = USB2_PORT_MID(OC_SKIP), |
| 33 | }" |
| 34 | register "usb3_ports" = "{ |
| 35 | [0] = USB3_PORT_DEFAULT(OC0), |
| 36 | [1] = USB3_PORT_DEFAULT(OC0), |
| 37 | [2] = USB3_PORT_DEFAULT(OC3), |
| 38 | [3] = USB3_PORT_DEFAULT(OC3), |
| 39 | [4] = USB3_PORT_DEFAULT(OC1), |
| 40 | [5] = USB3_PORT_DEFAULT(OC1), |
| 41 | [6] = USB3_PORT_DEFAULT(OC_SKIP), |
| 42 | [7] = USB3_PORT_DEFAULT(OC_SKIP), |
| 43 | [8] = USB3_PORT_DEFAULT(OC_SKIP), |
| 44 | [9] = USB3_PORT_DEFAULT(OC_SKIP), |
| 45 | }" |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 46 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 47 | device ref thermal on end |
| 48 | device ref heci1 on end |
| 49 | device ref sata on |
| 50 | register "SataSalpSupport" = "1" |
| 51 | register "SataPortsEnable" = "{ |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 52 | [0] = 1, |
| 53 | [1] = 1, |
| 54 | [2] = 1, |
| 55 | [3] = 1, |
| 56 | }" |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 57 | register "SataPortsHotPlug" = "{ |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 58 | [0] = 1, |
| 59 | [1] = 1, |
| 60 | [2] = 1, |
| 61 | [3] = 1, |
| 62 | }" |
| 63 | # DevSlp not supported |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 64 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 65 | device ref uart2 on end |
| 66 | device ref pcie_rp5 on |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 67 | register "PcieRpEnable[4]" = "1" |
| 68 | register "PcieRpLtrEnable[4]" = "1" |
| 69 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 70 | register "PcieRpClkSrcNumber[4]" = "11" |
| 71 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 72 | device ref pcie_rp6 on |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 73 | register "PcieRpEnable[5]" = "1" |
| 74 | register "PcieRpHotPlug[5]" = "1" |
| 75 | register "PcieRpLtrEnable[5]" = "1" |
| 76 | register "PcieRpAdvancedErrorReporting[5]" = "1" |
| 77 | register "PcieRpClkSrcNumber[5]" = "6" |
| 78 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 79 | device ref pcie_rp7 on |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 80 | register "PcieRpEnable[6]" = "1" |
| 81 | register "PcieRpLtrEnable[6]" = "1" |
| 82 | register "PcieRpAdvancedErrorReporting[6]" = "1" |
| 83 | register "PcieRpClkSrcNumber[6]" = "10" |
| 84 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 85 | device ref pcie_rp8 on |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 86 | register "PcieRpEnable[7]" = "1" |
| 87 | register "PcieRpHotPlug[7]" = "1" |
| 88 | register "PcieRpLtrEnable[7]" = "1" |
| 89 | register "PcieRpAdvancedErrorReporting[7]" = "1" |
| 90 | register "PcieRpClkSrcNumber[7]" = "12" |
| 91 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 92 | device ref lpc_espi on |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 93 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 94 | |
| 95 | # FIXME: Missing Super I/O HWM config |
| 96 | register "gen1_dec" = "0x000c0291" |
| 97 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 98 | device ref pmc on |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 99 | register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" |
| 100 | register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" |
| 101 | register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" |
| 102 | register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" |
| 103 | register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" |
| 104 | end |
Felix Singer | 3b5b9f4 | 2023-10-23 09:30:40 +0200 | [diff] [blame^] | 105 | device ref hda on end |
| 106 | device ref smbus on end |
| 107 | device ref fast_spi on end |
| 108 | device ref tracehub on |
Angel Pons | d8fcd42 | 2020-12-06 23:55:08 +0100 | [diff] [blame] | 109 | register "TraceHubMemReg0Size" = "2" |
| 110 | register "TraceHubMemReg1Size" = "2" |
| 111 | end |
| 112 | end |
| 113 | end |