| # SPDX-License-Identifier: GPL-2.0-only |
| |
| chip soc/intel/skylake |
| register "SerialIoDevMode" = "{ |
| [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ |
| }" |
| |
| register "eist_enable" = "1" |
| |
| device cpu_cluster 0 on end |
| device domain 0 on |
| subsystemid 0x103c 0x2b5e inherit |
| device ref peg0 on end |
| device ref igpu on end |
| device ref sa_thermal on end |
| device ref gmm on end |
| device ref south_xhci on |
| register "usb2_ports" = "{ |
| [0] = USB2_PORT_MID(OC0), |
| [1] = USB2_PORT_MID(OC0), |
| [2] = USB2_PORT_MID(OC4), |
| [3] = USB2_PORT_MID(OC4), |
| [4] = USB2_PORT_MID(OC2), |
| [5] = USB2_PORT_MID(OC2), |
| [6] = USB2_PORT_MID(OC0), |
| [7] = USB2_PORT_MID(OC0), |
| [8] = USB2_PORT_MID(OC0), |
| [9] = USB2_PORT_MID(OC0), |
| [10] = USB2_PORT_MID(OC1), |
| [11] = USB2_PORT_MID(OC1), |
| [12] = USB2_PORT_MID(OC_SKIP), |
| [13] = USB2_PORT_MID(OC_SKIP), |
| }" |
| register "usb3_ports" = "{ |
| [0] = USB3_PORT_DEFAULT(OC0), |
| [1] = USB3_PORT_DEFAULT(OC0), |
| [2] = USB3_PORT_DEFAULT(OC3), |
| [3] = USB3_PORT_DEFAULT(OC3), |
| [4] = USB3_PORT_DEFAULT(OC1), |
| [5] = USB3_PORT_DEFAULT(OC1), |
| [6] = USB3_PORT_DEFAULT(OC_SKIP), |
| [7] = USB3_PORT_DEFAULT(OC_SKIP), |
| [8] = USB3_PORT_DEFAULT(OC_SKIP), |
| [9] = USB3_PORT_DEFAULT(OC_SKIP), |
| }" |
| end |
| device ref thermal on end |
| device ref heci1 on end |
| device ref sata on |
| register "SataSalpSupport" = "1" |
| register "SataPortsEnable" = "{ |
| [0] = 1, |
| [1] = 1, |
| [2] = 1, |
| [3] = 1, |
| }" |
| register "SataPortsHotPlug" = "{ |
| [0] = 1, |
| [1] = 1, |
| [2] = 1, |
| [3] = 1, |
| }" |
| # DevSlp not supported |
| end |
| device ref uart2 on end |
| device ref pcie_rp5 on |
| register "PcieRpEnable[4]" = "1" |
| register "PcieRpLtrEnable[4]" = "1" |
| register "PcieRpAdvancedErrorReporting[4]" = "1" |
| register "PcieRpClkSrcNumber[4]" = "11" |
| end |
| device ref pcie_rp6 on |
| register "PcieRpEnable[5]" = "1" |
| register "PcieRpHotPlug[5]" = "1" |
| register "PcieRpLtrEnable[5]" = "1" |
| register "PcieRpAdvancedErrorReporting[5]" = "1" |
| register "PcieRpClkSrcNumber[5]" = "6" |
| end |
| device ref pcie_rp7 on |
| register "PcieRpEnable[6]" = "1" |
| register "PcieRpLtrEnable[6]" = "1" |
| register "PcieRpAdvancedErrorReporting[6]" = "1" |
| register "PcieRpClkSrcNumber[6]" = "10" |
| end |
| device ref pcie_rp8 on |
| register "PcieRpEnable[7]" = "1" |
| register "PcieRpHotPlug[7]" = "1" |
| register "PcieRpLtrEnable[7]" = "1" |
| register "PcieRpAdvancedErrorReporting[7]" = "1" |
| register "PcieRpClkSrcNumber[7]" = "12" |
| end |
| device ref lpc_espi on |
| register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| |
| # FIXME: Missing Super I/O HWM config |
| register "gen1_dec" = "0x000c0291" |
| end |
| device ref pmc on |
| register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" |
| register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" |
| register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" |
| register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" |
| register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" |
| end |
| device ref hda on end |
| device ref smbus on end |
| device ref fast_spi on end |
| device ref tracehub on |
| register "TraceHubMemReg0Size" = "2" |
| register "TraceHubMemReg1Size" = "2" |
| end |
| end |
| end |