Patrick Georgi | 11f0079 | 2020-03-04 15:10:45 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 2 | |
| 3 | #include <cpu/x86/mtrr.h> |
| 4 | #include <cpu/x86/cr.h> |
Arthur Heymans | a6a2f93 | 2019-11-25 19:58:36 +0100 | [diff] [blame] | 5 | #include <cpu/x86/cache.h> |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 6 | |
Elyes Haouas | 3b3bb7c | 2023-02-08 12:49:33 +0100 | [diff] [blame^] | 7 | /* Place the stack in the bss section. It's not necessary to define it in |
Arthur Heymans | 5315e96 | 2021-05-14 11:22:31 +0200 | [diff] [blame] | 8 | * the linker script. */ |
| 9 | .section .bss, "aw", @nobits |
| 10 | .global _stack |
| 11 | .global _estack |
| 12 | .global _stack_size |
| 13 | |
| 14 | _stack: |
| 15 | .space CONFIG_STACK_SIZE |
| 16 | _estack: |
| 17 | .set _stack_size, _estack - _stack |
| 18 | |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 19 | .text |
| 20 | .global _start |
| 21 | _start: |
Aaron Durbin | 028e18f | 2017-06-23 11:14:58 -0500 | [diff] [blame] | 22 | /* Assume stack alignment doesn't matter here as chipset_teardown_car |
| 23 | is expected to be implemented in assembly. */ |
| 24 | |
Hannah Williams | d3c0c0c | 2018-04-27 09:09:04 -0700 | [diff] [blame] | 25 | /* Migrate GDT to this text segment */ |
Patrick Rudolph | adcf782 | 2020-08-27 20:50:18 +0200 | [diff] [blame] | 26 | #if ENV_X86_64 |
Patrick Rudolph | 8daa12f | 2018-12-26 15:12:32 +0100 | [diff] [blame] | 27 | call gdt_init64 |
| 28 | #else |
Hannah Williams | d3c0c0c | 2018-04-27 09:09:04 -0700 | [diff] [blame] | 29 | call gdt_init |
Patrick Rudolph | 8daa12f | 2018-12-26 15:12:32 +0100 | [diff] [blame] | 30 | #endif |
Hannah Williams | d3c0c0c | 2018-04-27 09:09:04 -0700 | [diff] [blame] | 31 | |
Patrick Rudolph | adcf782 | 2020-08-27 20:50:18 +0200 | [diff] [blame] | 32 | #if ENV_X86_64 |
Patrick Rudolph | d023909 | 2021-06-11 21:24:10 +0200 | [diff] [blame] | 33 | mov %rdi, %rax |
| 34 | movabs %rax, _cbmem_top_ptr |
Arthur Heymans | 7c9a0e8 | 2019-10-23 17:02:50 +0200 | [diff] [blame] | 35 | #else |
| 36 | /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ |
| 37 | movl 4(%esp), %eax |
| 38 | movl %eax, _cbmem_top_ptr |
| 39 | #endif |
Arthur Heymans | a6a2f93 | 2019-11-25 19:58:36 +0100 | [diff] [blame] | 40 | /* Make sure _cbmem_top_ptr hits dram before invd */ |
| 41 | movl $1, %eax |
| 42 | cpuid |
| 43 | btl $CPUID_FEATURE_CLFLUSH_BIT, %edx |
Arthur Heymans | 014c889 | 2020-08-29 08:21:49 +0200 | [diff] [blame] | 44 | jnc skip_clflush |
Patrick Rudolph | adcf782 | 2020-08-27 20:50:18 +0200 | [diff] [blame] | 45 | #if ENV_X86_64 |
Patrick Rudolph | feab8bb | 2021-12-03 17:12:08 +0100 | [diff] [blame] | 46 | movabs $_cbmem_top_ptr, %rax |
Patrick Rudolph | d023909 | 2021-06-11 21:24:10 +0200 | [diff] [blame] | 47 | clflush (%rax) |
| 48 | #else |
Arthur Heymans | a6a2f93 | 2019-11-25 19:58:36 +0100 | [diff] [blame] | 49 | clflush _cbmem_top_ptr |
Patrick Rudolph | d023909 | 2021-06-11 21:24:10 +0200 | [diff] [blame] | 50 | #endif |
Arthur Heymans | 7c9a0e8 | 2019-10-23 17:02:50 +0200 | [diff] [blame] | 51 | |
Arthur Heymans | a6a2f93 | 2019-11-25 19:58:36 +0100 | [diff] [blame] | 52 | skip_clflush: |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 53 | /* chipset_teardown_car() is expected to disable cache-as-ram. */ |
| 54 | call chipset_teardown_car |
| 55 | |
| 56 | /* Enable caching if not already enabled. */ |
Patrick Rudolph | adcf782 | 2020-08-27 20:50:18 +0200 | [diff] [blame] | 57 | #if ENV_X86_64 |
Patrick Rudolph | 8daa12f | 2018-12-26 15:12:32 +0100 | [diff] [blame] | 58 | mov %cr0, %rax |
| 59 | and $(~(CR0_CD | CR0_NW)), %eax |
| 60 | mov %rax, %cr0 |
| 61 | #else |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 62 | mov %cr0, %eax |
| 63 | and $(~(CR0_CD | CR0_NW)), %eax |
| 64 | mov %eax, %cr0 |
Arthur Heymans | 46b409d | 2021-05-14 13:19:43 +0200 | [diff] [blame] | 65 | #endif |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 66 | /* Ensure cache is clean. */ |
| 67 | invd |
| 68 | |
Arthur Heymans | 5315e96 | 2021-05-14 11:22:31 +0200 | [diff] [blame] | 69 | movl $_estack, %esp |
Aaron Durbin | 028e18f | 2017-06-23 11:14:58 -0500 | [diff] [blame] | 70 | /* Align stack to 16 bytes at call instruction. */ |
| 71 | andl $0xfffffff0, %esp |
Arthur Heymans | 5315e96 | 2021-05-14 11:22:31 +0200 | [diff] [blame] | 72 | |
Arthur Heymans | 46b409d | 2021-05-14 13:19:43 +0200 | [diff] [blame] | 73 | /* Call this in assembly as some platforms like to mess with the bootflow and |
| 74 | call into main directly from chipset_teardown_car. */ |
| 75 | call postcar_mtrr_setup |
| 76 | |
Aaron Durbin | 6b0cebc | 2016-09-16 16:15:14 -0500 | [diff] [blame] | 77 | /* Call into main for postcar. */ |
| 78 | call main |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 79 | /* Should never return. */ |
| 80 | 1: |
| 81 | jmp 1b |