Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BRASWELL |
| 2 | bool |
| 3 | help |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 4 | Braswell M/D part support. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 5 | |
| 6 | if SOC_INTEL_BRASWELL |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 11 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 14 | select BACKUP_DEFAULT_SMM_REGION |
| 15 | select CACHE_MRC_SETTINGS |
Alexandru Gagniuc | 27fea06 | 2015-08-29 20:00:24 -0700 | [diff] [blame^] | 16 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | select COLLECT_TIMESTAMPS |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 18 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 19 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 20 | select HAS_PRECBMEM_TIMESTAMP_REGION |
| 21 | select HAVE_MONOTONIC_TIMER |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | select HAVE_SMI_HANDLER |
| 23 | select HAVE_HARD_RESET |
| 24 | select MMCONF_SUPPORT |
| 25 | select MMCONF_SUPPORT_DEFAULT |
| 26 | select RELOCATABLE_MODULES |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 27 | select PARALLEL_MP |
| 28 | select PCIEXP_ASPM |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 29 | select PCIEXP_CLK_PM |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | select PCIEXP_COMMON_CLOCK |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 31 | select PCIEXP_L1_SUB_STATE |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 32 | select PLATFORM_USES_FSP1_1 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | select REG_SCRIPT |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 34 | select SOC_INTEL_COMMON |
| 35 | select SOC_INTEL_COMMON_FSP_RAM_INIT |
| 36 | select SOC_INTEL_COMMON_FSP_ROMSTAGE |
| 37 | select SOC_INTEL_COMMON_RESET |
| 38 | select SOC_INTEL_COMMON_STACK |
| 39 | select SOC_INTEL_COMMON_STAGE_CACHE |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 40 | select SMM_TSEG |
| 41 | select SMP |
| 42 | select SPI_FLASH |
| 43 | select SSE2 |
| 44 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 45 | select TSC_CONSTANT_RATE |
| 46 | select TSC_MONOTONIC_TIMER |
| 47 | select TSC_SYNC_MFENCE |
| 48 | select UDELAY_TSC |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 49 | select USE_GENERIC_FSP_CAR_INC |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 50 | |
| 51 | config BOOTBLOCK_CPU_INIT |
| 52 | string |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 53 | default "soc/intel/braswell/bootblock/bootblock.c" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 54 | |
| 55 | config MMCONF_BASE_ADDRESS |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 56 | hex "PCIe CFG Base Address" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 57 | default 0xe0000000 |
| 58 | |
| 59 | config MAX_CPUS |
| 60 | int |
| 61 | default 4 |
| 62 | |
| 63 | config CPU_ADDR_BITS |
| 64 | int |
| 65 | default 36 |
| 66 | |
| 67 | config SMM_TSEG_SIZE |
| 68 | hex |
| 69 | default 0x800000 |
| 70 | |
| 71 | config SMM_RESERVED_SIZE |
| 72 | hex |
| 73 | default 0x100000 |
| 74 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 75 | # Cache As RAM region layout: |
| 76 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 77 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 78 | # | Stack |\ |
| 79 | # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 80 | # | v |/ |
| 81 | # +-------------+ |
| 82 | # | ^ | |
| 83 | # | | | |
| 84 | # | CAR Globals | |
| 85 | # +-------------+ DCACHE_RAM_BASE |
| 86 | # |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 87 | |
| 88 | config DCACHE_RAM_BASE |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 89 | hex "Temporary RAM Base Address" |
| 90 | default 0xfef00000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 91 | |
| 92 | config DCACHE_RAM_SIZE |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 93 | hex "Temporary RAM Size" |
| 94 | default 0x4000 |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 95 | help |
| 96 | The size of the cache-as-ram region required during bootblock |
| 97 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 98 | must add up to a power of 2. |
| 99 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 100 | config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 101 | hex |
| 102 | default 0x800 |
| 103 | help |
| 104 | The amount of anticipated stack usage from the data cache |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 105 | during pre-ram rom stage execution. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 106 | |
| 107 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 108 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 109 | default n |
| 110 | depends on RELOCATABLE_RAMSTAGE |
| 111 | help |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 112 | The haswell romstage code caches the loaded ramstage program |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 113 | in SMM space. On S3 wake the romstage will copy over a fresh |
| 114 | ramstage that was cached in the SMM space. This option determines |
| 115 | the action to take when the ramstage cache is invalid. If selected |
| 116 | the system will reset otherwise the ramstage will be reloaded from |
| 117 | cbfs. |
| 118 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 119 | config LOCK_MANAGEMENT_ENGINE |
| 120 | bool "Lock Management Engine section" |
| 121 | default n |
| 122 | help |
| 123 | The Intel Management Engine supports preventing write accesses |
| 124 | from the host to the Management Engine section in the firmware |
| 125 | descriptor. If the ME section is locked, it can only be overwritten |
| 126 | with an external SPI flash programmer. You will want this if you |
| 127 | want to increase security of your ROM image once you are sure |
| 128 | that the ME firmware is no longer going to change. |
| 129 | |
| 130 | If unsure, say N. |
| 131 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 132 | config ENABLE_BUILTIN_COM1 |
| 133 | bool "Enable builtin COM1 Serial Port" |
| 134 | default n |
| 135 | help |
| 136 | The PMC has a legacy COM1 serial port. Choose this option to |
| 137 | configure the pads and enable it. This serial port can be used for |
| 138 | the debug console. |
| 139 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 140 | config HAVE_IFD_BIN |
| 141 | bool |
| 142 | default y |
| 143 | |
| 144 | config BUILD_WITH_FAKE_IFD |
| 145 | bool "Build with a fake IFD" |
| 146 | default y if !HAVE_IFD_BIN |
| 147 | help |
| 148 | If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| 149 | board, you can select this option and coreboot will build without it. |
| 150 | Though, the resulting coreboot.rom will not contain all parts required |
| 151 | to get coreboot running on your board. You can however write only the |
| 152 | BIOS section to your board's flash ROM and keep the other sections |
| 153 | untouched. Unfortunately the current version of flashrom doesn't |
| 154 | support this yet. But there is a patch pending [1]. |
| 155 | |
| 156 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 157 | was built with a fake IFD. It just won't work. |
| 158 | |
| 159 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 160 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 161 | config HAVE_ME_BIN |
| 162 | bool "Add Intel Management Engine firmware" |
| 163 | default y |
| 164 | help |
| 165 | The Intel processor in the selected system requires a special firmware |
| 166 | for an integrated controller called Management Engine (ME). The ME |
| 167 | firmware might be provided in coreboot's 3rdparty/blobs repository. If |
| 168 | not and if you don't have the firmware elsewhere, you can still |
| 169 | build coreboot without it. In this case however, you'll have to make |
| 170 | sure that you don't overwrite your ME firmware on your flash ROM. |
| 171 | |
| 172 | config IED_REGION_SIZE |
| 173 | hex |
| 174 | default 0x400000 |
| 175 | |
| 176 | config IFD_BIN_PATH |
| 177 | string "Path to intel firmware descriptor" |
| 178 | depends on !BUILD_WITH_FAKE_IFD |
| 179 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
| 180 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 181 | config IFD_BIOS_SECTION |
| 182 | depends on BUILD_WITH_FAKE_IFD |
| 183 | string |
| 184 | default "" |
| 185 | |
| 186 | config IFD_ME_SECTION |
| 187 | depends on BUILD_WITH_FAKE_IFD |
| 188 | string |
| 189 | default "" |
| 190 | |
| 191 | config IFD_PLATFORM_SECTION |
| 192 | depends on BUILD_WITH_FAKE_IFD |
| 193 | string |
| 194 | default "" |
| 195 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 196 | config ME_BIN_PATH |
| 197 | string "Path to management engine firmware" |
| 198 | depends on HAVE_ME_BIN |
| 199 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 200 | |
| 201 | endif |