Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BROADWELL |
| 2 | bool |
| 3 | help |
| 4 | Intel Broadwell and Haswell ULT support. |
| 5 | |
| 6 | if SOC_INTEL_BROADWELL |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 11 | select ARCH_VERSTAGE_X86_32 |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_RAMSTAGE_X86_32 |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | select BACKUP_DEFAULT_SMM_REGION |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | select CACHE_MRC_SETTINGS |
Duncan Laurie | f059b24 | 2015-01-15 15:42:43 -0800 | [diff] [blame] | 16 | select MRC_SETTINGS_PROTECT |
Alexandru Gagniuc | 27fea06 | 2015-08-29 20:00:24 -0700 | [diff] [blame] | 17 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 18 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Kyösti Mälkki | 4851bf2 | 2014-12-27 12:57:06 +0200 | [diff] [blame] | 19 | select SUPPORT_CPU_UCODE_IN_CBFS |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 20 | select HAVE_MONOTONIC_TIMER |
| 21 | select HAVE_SMI_HANDLER |
| 22 | select HAVE_HARD_RESET |
| 23 | select HAVE_USBDEBUG |
| 24 | select IOAPIC |
| 25 | select MMCONF_SUPPORT |
| 26 | select MMCONF_SUPPORT_DEFAULT |
| 27 | select RELOCATABLE_MODULES |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 28 | select RELOCATABLE_RAMSTAGE |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | select REG_SCRIPT |
| 30 | select PARALLEL_MP |
| 31 | select PCIEXP_ASPM |
| 32 | select PCIEXP_COMMON_CLOCK |
Kane Chen | 9604474 | 2014-10-01 13:22:52 +0800 | [diff] [blame] | 33 | select PCIEXP_CLK_PM |
Kenji Chen | b71d9b8 | 2014-10-10 03:08:15 +0800 | [diff] [blame] | 34 | select PCIEXP_L1_SUB_STATE |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 35 | select SMM_TSEG |
| 36 | select SMP |
| 37 | select SPI_FLASH |
| 38 | select SSE2 |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 39 | select SUPPORT_CPU_UCODE_IN_CBFS |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 40 | select TSC_CONSTANT_RATE |
| 41 | select TSC_SYNC_MFENCE |
| 42 | select UDELAY_TSC |
Stefan Reinauer | 9616f3c | 2015-04-29 10:45:22 -0700 | [diff] [blame] | 43 | select SOC_INTEL_COMMON |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 44 | |
| 45 | config BOOTBLOCK_CPU_INIT |
| 46 | string |
| 47 | default "soc/intel/broadwell/bootblock/cpu.c" |
| 48 | |
| 49 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 50 | string |
| 51 | default "soc/intel/broadwell/bootblock/systemagent.c" |
| 52 | |
| 53 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 54 | string |
| 55 | default "soc/intel/broadwell/bootblock/pch.c" |
| 56 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 57 | |
| 58 | config MMCONF_BASE_ADDRESS |
| 59 | hex |
| 60 | default 0xf0000000 |
| 61 | |
| 62 | config SERIAL_CPU_INIT |
| 63 | bool |
| 64 | default n |
| 65 | |
| 66 | config SMM_TSEG_SIZE |
| 67 | hex |
| 68 | default 0x800000 |
| 69 | |
| 70 | config IED_REGION_SIZE |
| 71 | hex |
| 72 | default 0x400000 |
| 73 | |
| 74 | config SMM_RESERVED_SIZE |
| 75 | hex |
| 76 | default 0x100000 |
| 77 | |
| 78 | config VGA_BIOS_ID |
| 79 | string |
| 80 | default "8086,0406" |
| 81 | |
| 82 | config CACHE_MRC_SIZE_KB |
| 83 | int |
| 84 | default 512 |
| 85 | |
| 86 | config DCACHE_RAM_BASE |
| 87 | hex |
| 88 | default 0xff7c0000 |
| 89 | |
| 90 | config DCACHE_RAM_SIZE |
| 91 | hex |
| 92 | default 0x10000 |
| 93 | help |
| 94 | The size of the cache-as-ram region required during bootblock |
| 95 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 96 | must add up to a power of 2. |
| 97 | |
| 98 | config DCACHE_RAM_MRC_VAR_SIZE |
| 99 | hex |
| 100 | default 0x30000 |
| 101 | help |
| 102 | The amount of cache-as-ram region required by the reference code. |
| 103 | |
| 104 | config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 105 | hex |
| 106 | default 0x2000 |
| 107 | help |
| 108 | The amount of anticipated stack usage from the data cache |
| 109 | during pre-ram rom stage execution. |
| 110 | |
| 111 | config HAVE_MRC |
| 112 | bool "Add a Memory Reference Code binary" |
| 113 | help |
| 114 | Select this option to add a Memory Reference Code binary to |
| 115 | the resulting coreboot image. |
| 116 | |
| 117 | Note: Without this binary coreboot will not work |
| 118 | |
| 119 | if HAVE_MRC |
| 120 | |
| 121 | config MRC_FILE |
| 122 | string "Intel Memory Reference Code path and filename" |
| 123 | depends on HAVE_MRC |
| 124 | default "mrc.bin" |
| 125 | help |
| 126 | The filename of the file to use as Memory Reference Code binary. |
| 127 | |
| 128 | config MRC_BIN_ADDRESS |
| 129 | hex |
| 130 | default 0xfffa0000 |
| 131 | |
| 132 | config CACHE_MRC_SETTINGS |
| 133 | bool "Save cached MRC settings" |
| 134 | default y |
| 135 | |
| 136 | endif # HAVE_MRC |
| 137 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 138 | config PRE_GRAPHICS_DELAY |
| 139 | int "Graphics initialization delay in ms" |
| 140 | default 0 |
| 141 | help |
| 142 | On some systems, coreboot boots so fast that connected monitors |
| 143 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 144 | VBIOS. On those systems we need to wait for a bit before executing |
| 145 | the VBIOS. |
| 146 | |
| 147 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 148 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 149 | default n |
| 150 | depends on RELOCATABLE_RAMSTAGE |
| 151 | help |
| 152 | The romstage code caches the loaded ramstage program in SMM space. |
| 153 | On S3 wake the romstage will copy over a fresh ramstage that was |
| 154 | cached in the SMM space. This option determines the action to take |
| 155 | when the ramstage cache is invalid. If selected the system will |
| 156 | reset otherwise the ramstage will be reloaded from cbfs. |
| 157 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 158 | config INTEL_PCH_UART_CONSOLE |
| 159 | bool "Use Serial IO UART for console" |
| 160 | default n |
Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 161 | select DRIVERS_UART_8250MEM |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 162 | |
| 163 | config INTEL_PCH_UART_CONSOLE_NUMBER |
| 164 | hex "Serial IO UART number to use for console" |
| 165 | default "0x0" |
| 166 | depends on INTEL_PCH_UART_CONSOLE |
| 167 | |
| 168 | config TTYS0_BASE |
| 169 | hex |
| 170 | default 0xd6000000 |
| 171 | depends on INTEL_PCH_UART_CONSOLE |
| 172 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 173 | config EHCI_BAR |
| 174 | hex |
| 175 | default 0xd8000000 |
| 176 | |
| 177 | config EHCI_DEBUG_OFFSET |
| 178 | hex |
| 179 | default 0xa0 |
| 180 | |
| 181 | config SERIRQ_CONTINUOUS_MODE |
| 182 | bool |
| 183 | default y |
| 184 | help |
| 185 | If you set this option to y, the serial IRQ machine will be |
| 186 | operated in continuous mode. |
Patrick Georgi | e6e9493 | 2015-06-22 22:26:45 +0200 | [diff] [blame] | 187 | |
| 188 | config HAVE_REFCODE_BLOB |
| 189 | depends on ARCH_X86 |
| 190 | bool "An external reference code blob should be put into cbfs." |
| 191 | default n |
| 192 | help |
| 193 | The reference code blob will be placed into cbfs. |
| 194 | |
| 195 | if HAVE_REFCODE_BLOB |
| 196 | |
| 197 | config REFCODE_BLOB_FILE |
| 198 | string "Path and filename to reference code blob." |
| 199 | default "refcode.elf" |
| 200 | help |
| 201 | The path and filename to the file to be added to cbfs. |
| 202 | |
| 203 | endif # HAVE_REFCODE_BLOB |
| 204 | |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 205 | config HAVE_ME_BIN |
| 206 | bool "Add Intel Management Engine firmware" |
| 207 | default y |
| 208 | help |
| 209 | The Intel processor in the selected system requires a special firmware |
| 210 | for an integrated controller called Management Engine (ME). The ME |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 211 | firmware might be provided in coreboot's 3rdparty/blobs repository. If |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 212 | not and if you don't have the firmware elsewhere, you can still |
| 213 | build coreboot without it. In this case however, you'll have to make |
| 214 | sure that you don't overwrite your ME firmware on your flash ROM. |
| 215 | |
| 216 | config ME_BIN_PATH |
| 217 | string "Path to management engine firmware" |
| 218 | depends on HAVE_ME_BIN |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 219 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 220 | |
| 221 | config HAVE_IFD_BIN |
Patrick Georgi | 405bd69 | 2015-04-30 21:31:17 +0200 | [diff] [blame] | 222 | bool "Use Intel Firmware Descriptor from existing binary" |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 223 | default n |
| 224 | |
| 225 | config BUILD_WITH_FAKE_IFD |
| 226 | bool "Build with a fake IFD" |
| 227 | default y if !HAVE_IFD_BIN |
| 228 | help |
| 229 | If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| 230 | board, you can select this option and coreboot will build without it. |
| 231 | Though, the resulting coreboot.rom will not contain all parts required |
| 232 | to get coreboot running on your board. You can however write only the |
| 233 | BIOS section to your board's flash ROM and keep the other sections |
| 234 | untouched. Unfortunately the current version of flashrom doesn't |
| 235 | support this yet. But there is a patch pending [1]. |
| 236 | |
| 237 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 238 | was built with a fake IFD. It just won't work. |
| 239 | |
| 240 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 241 | |
| 242 | config IFD_BIOS_SECTION |
| 243 | depends on BUILD_WITH_FAKE_IFD |
| 244 | string |
| 245 | default "" |
| 246 | |
| 247 | config IFD_ME_SECTION |
| 248 | depends on BUILD_WITH_FAKE_IFD |
| 249 | string |
| 250 | default "" |
| 251 | |
| 252 | config IFD_PLATFORM_SECTION |
| 253 | depends on BUILD_WITH_FAKE_IFD |
| 254 | string |
| 255 | default "" |
| 256 | |
| 257 | config IFD_BIN_PATH |
| 258 | string "Path to intel firmware descriptor" |
| 259 | depends on !BUILD_WITH_FAKE_IFD |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 260 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 261 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 262 | config LOCK_MANAGEMENT_ENGINE |
| 263 | bool "Lock Management Engine section" |
| 264 | default n |
| 265 | help |
| 266 | The Intel Management Engine supports preventing write accesses |
| 267 | from the host to the Management Engine section in the firmware |
| 268 | descriptor. If the ME section is locked, it can only be overwritten |
| 269 | with an external SPI flash programmer. You will want this if you |
| 270 | want to increase security of your ROM image once you are sure |
| 271 | that the ME firmware is no longer going to change. |
| 272 | |
| 273 | If unsure, say N. |
| 274 | |
Aaron Durbin | 3953e39 | 2015-09-03 00:41:29 -0500 | [diff] [blame^] | 275 | config CHIPSET_BOOTBLOCK_INCLUDE |
| 276 | string |
| 277 | default "soc/intel/broadwell/bootblock/timestamp.inc" |
| 278 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 279 | endif |