src/soc/intel/broadwell/Kconfig

config SOC_INTEL_BROADWELL
	bool
	help
	  Intel Broadwell and Haswell ULT support.

if SOC_INTEL_BROADWELL

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_VERSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_RAMSTAGE_X86_32
	select ALT_CBFS_LOAD_PAYLOAD
	select ALWAYS_LOAD_OPROM
	select BACKUP_DEFAULT_SMM_REGION
	select CACHE_MRC_BIN
	select CACHE_MRC_SETTINGS
	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
	select CACHE_ROM
	select CAR_MIGRATION
	select COLLECT_TIMESTAMPS
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select SUPPORT_CPU_UCODE_IN_CBFS
	select HAVE_MONOTONIC_TIMER
	select HAVE_SMI_HANDLER
	select HAVE_HARD_RESET
	select HAVE_USBDEBUG
	select IOAPIC
	select MMCONF_SUPPORT
	select MMCONF_SUPPORT_DEFAULT
	select RELOCATABLE_MODULES
	select RELOCATABLE_RAMSTAGE
	select REG_SCRIPT
	select PARALLEL_MP
	select PCIEXP_ASPM
	select PCIEXP_COMMON_CLOCK
	select PCIEXP_CLK_PM
	select PCIEXP_L1_SUB_STATE
	select SMM_MODULES
	select SMM_TSEG
	select SMP
	select SPI_FLASH
	select SSE2
	select SUPPORT_CPU_UCODE_IN_CBFS
	select TSC_CONSTANT_RATE
	select TSC_SYNC_MFENCE
	select UDELAY_TSC
	select PER_DEVICE_ACPI_TABLES

config BOOTBLOCK_CPU_INIT
	string
	default "soc/intel/broadwell/bootblock/cpu.c"

config BOOTBLOCK_NORTHBRIDGE_INIT
	string
	default "soc/intel/broadwell/bootblock/systemagent.c"

config BOOTBLOCK_SOUTHBRIDGE_INIT
	string
	default "soc/intel/broadwell/bootblock/pch.c"


config MMCONF_BASE_ADDRESS
	hex
	default 0xf0000000

config SERIAL_CPU_INIT
	bool
	default n

config SMM_TSEG_SIZE
	hex
	default 0x800000

config IED_REGION_SIZE
	hex
	default 0x400000

config SMM_RESERVED_SIZE
	hex
	default 0x100000

config VGA_BIOS_ID
	string
	default "8086,0406"

config CACHE_MRC_SIZE_KB
	int
	default 512

config DCACHE_RAM_BASE
	hex
	default 0xff7c0000

config DCACHE_RAM_SIZE
	hex
	default 0x10000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
	  must add up to a power of 2.

config DCACHE_RAM_MRC_VAR_SIZE
	hex
	default 0x30000
	help
	  The amount of cache-as-ram region required by the reference code.

config DCACHE_RAM_ROMSTAGE_STACK_SIZE
	hex
	default 0x2000
	help
	  The amount of anticipated stack usage from the data cache
	  during pre-ram rom stage execution.

config HAVE_MRC
	bool "Add a Memory Reference Code binary"
	help
	  Select this option to add a Memory Reference Code binary to
	  the resulting coreboot image.

	  Note: Without this binary coreboot will not work

if HAVE_MRC

config MRC_FILE
	string "Intel Memory Reference Code path and filename"
	depends on HAVE_MRC
	default "mrc.bin"
	help
	  The filename of the file to use as Memory Reference Code binary.

config MRC_BIN_ADDRESS
	hex
	default 0xfffa0000

config CACHE_MRC_SETTINGS
	bool "Save cached MRC settings"
	default y

endif # HAVE_MRC

config CBFS_SIZE
	hex "Size of CBFS filesystem in ROM"
	default 0x100000
	help
	  The firmware image has to store more than just coreboot, including:
	   - a firmware descriptor
	   - Intel Management Engine firmware
	   - MRC cache information
	  This option allows to limit the size of the CBFS portion in the
	  firmware image.

config PRE_GRAPHICS_DELAY
	int "Graphics initialization delay in ms"
	default 0
	help
	  On some systems, coreboot boots so fast that connected monitors
	  (mostly TVs) won't be able to wake up fast enough to talk to the
	  VBIOS. On those systems we need to wait for a bit before executing
	  the VBIOS.

config RESET_ON_INVALID_RAMSTAGE_CACHE
	bool "Reset the system on S3 wake when ramstage cache invalid."
	default n
	depends on RELOCATABLE_RAMSTAGE
	help
	  The romstage code caches the loaded ramstage program in SMM space.
	  On S3 wake the romstage will copy over a fresh ramstage that was
	  cached in the SMM space. This option determines the action to take
	  when the ramstage cache is invalid. If selected the system will
	  reset otherwise the ramstage will be reloaded from cbfs.

config MONOTONIC_TIMER_MSR
	def_bool y
	select HAVE_MONOTONIC_TIMER
	help
	  Provide a monotonic timer using the 24MHz MSR counter.

config INTEL_PCH_UART_CONSOLE
	bool "Use Serial IO UART for console"
	default n
	select HAVE_UART_MEMORY_MAPPED
	select CONSOLE_SERIAL8250MEM
	depends on !CONFIG_DRIVERS_OXFORD_OXPCIE

config INTEL_PCH_UART_CONSOLE_NUMBER
	hex "Serial IO UART number to use for console"
	default "0x0"
	depends on INTEL_PCH_UART_CONSOLE

config TTYS0_BASE
	hex
	default 0xd6000000
	depends on INTEL_PCH_UART_CONSOLE

config EHCI_BAR
	hex
	default 0xd8000000

config EHCI_DEBUG_OFFSET
	hex
	default 0xa0

config SERIRQ_CONTINUOUS_MODE
	bool
	default y
	help
	  If you set this option to y, the serial IRQ machine will be
	  operated in continuous mode.
config HAVE_ME_BIN
	bool "Add Intel Management Engine firmware"
	default y
	help
	  The Intel processor in the selected system requires a special firmware
	  for an integrated controller called Management Engine (ME). The ME
	  firmware might be provided in coreboot's 3rdparty repository. If
	  not and if you don't have the firmware elsewhere, you can still
	  build coreboot without it. In this case however, you'll have to make
	  sure that you don't overwrite your ME firmware on your flash ROM.

config ME_BIN_PATH
	string "Path to management engine firmware"
	depends on HAVE_ME_BIN
	default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"

config HAVE_IFD_BIN
	bool
	default n

config BUILD_WITH_FAKE_IFD
	bool "Build with a fake IFD"
	default y if !HAVE_IFD_BIN
	help
	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
	  board, you can select this option and coreboot will build without it.
	  Though, the resulting coreboot.rom will not contain all parts required
	  to get coreboot running on your board. You can however write only the
	  BIOS section to your board's flash ROM and keep the other sections
	  untouched. Unfortunately the current version of flashrom doesn't
	  support this yet. But there is a patch pending [1].

	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
		   was built with a fake IFD. It just won't work.

	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

config IFD_BIOS_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_ME_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_PLATFORM_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_BIN_PATH
	string "Path to intel firmware descriptor"
	depends on !BUILD_WITH_FAKE_IFD
	default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"

config ME_MBP_CLEAR_LATE
	bool "Defer wait for ME MBP Cleared"
	default y
	help
	  If you set this option to y, the Management Engine driver
	  will defer waiting for the MBP Cleared indicator until the
	  finalize step.  This can speed up boot time if the ME takes
	  a long time to indicate this status.

config LOCK_MANAGEMENT_ENGINE
	bool "Lock Management Engine section"
	default n
	help
	  The Intel Management Engine supports preventing write accesses
	  from the host to the Management Engine section in the firmware
	  descriptor. If the ME section is locked, it can only be overwritten
	  with an external SPI flash programmer. You will want this if you
	  want to increase security of your ROM image once you are sure
	  that the ME firmware is no longer going to change.

	  If unsure, say N.

endif