Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Elyes HAOUAS | 8c905a8 | 2019-02-07 09:00:47 +0100 | [diff] [blame] | 20 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
Elyes HAOUAS | 8c905a8 | 2019-02-07 09:00:47 +0100 | [diff] [blame] | 22 | #include <cpu/x86/lapic.h> |
| 23 | #include <cpu/x86/msr.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <halt.h> |
Vladimir Serbinenko | a50478f | 2016-02-10 03:03:41 +0100 | [diff] [blame] | 26 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Elyes HAOUAS | 8c905a8 | 2019-02-07 09:00:47 +0100 | [diff] [blame] | 27 | #include <northbridge/intel/sandybridge/raminit.h> |
| 28 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 29 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 30 | #include <southbridge/intel/common/gpio.h> |
Elyes HAOUAS | e051dc0 | 2018-08-06 10:55:59 +0200 | [diff] [blame] | 31 | #include <superio/winbond/common/winbond.h> |
Elyes HAOUAS | 8c905a8 | 2019-02-07 09:00:47 +0100 | [diff] [blame] | 32 | #include <timestamp.h> |
| 33 | |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 34 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 35 | void pch_enable_lpc(void) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 36 | { |
| 37 | /* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */ |
| 38 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070); |
| 39 | |
| 40 | /* Enable KBC on 0x06/0x64 (KBC), |
| 41 | * EC on 0x62/0x66 (MC), |
| 42 | * EC on 0x20c-0x20f (GAMEH), |
| 43 | * Super I/O on 0x2e/0x2f (CNF1), |
| 44 | * COM1/COM3 decode ranges. */ |
| 45 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 46 | KBC_LPC_EN | MC_LPC_EN | |
| 47 | CNF1_LPC_EN | GAMEH_LPC_EN | |
| 48 | COMA_LPC_EN | COMB_LPC_EN); |
| 49 | } |
| 50 | |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 51 | void mainboard_rcba_config(void) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 52 | { |
| 53 | u32 reg32; |
| 54 | |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 55 | /* Disable unused devices (board specific) */ |
| 56 | reg32 = RCBA32(FD); |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 57 | /* Disable PCI bridge so MRC does not probe this bus */ |
| 58 | reg32 |= PCH_DISABLE_P2P; |
| 59 | RCBA32(FD) = reg32; |
| 60 | } |
| 61 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 62 | void mainboard_config_superio(void) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 63 | { |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 64 | int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */ |
| 65 | int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */ |
Antonello Dettori | 82fcc1a | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 66 | pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); |
Elyes HAOUAS | e051dc0 | 2018-08-06 10:55:59 +0200 | [diff] [blame] | 67 | pnp_enter_conf_state(dev); |
Nico Huber | 40f9ce9 | 2013-10-22 11:07:23 +0200 | [diff] [blame] | 68 | pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ |
| 69 | pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ |
| 70 | pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are |
| 71 | GPIO27, 26, 25, 24 */ |
| 72 | pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32, |
| 73 | Pins 78~85 are UART B */ |
| 74 | pnp_write_config(dev, 0x2d, 0x00); /* Pins 67, 68, 70~73, 75, 77 are |
| 75 | GPIO57~50 */ |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 76 | pnp_set_logical_device(dev); |
| 77 | /* Values can only be changed, when devices are enabled. */ |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 78 | pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */ |
Nico Huber | 40f9ce9 | 2013-10-22 11:07:23 +0200 | [diff] [blame] | 79 | pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */ |
Nico Huber | a90c785 | 2015-04-15 13:46:08 +0200 | [diff] [blame] | 80 | pnp_write_config(dev, 0xf3, 0x40); /* Disable suspend LED during normal operation */ |
Elyes HAOUAS | e051dc0 | 2018-08-06 10:55:59 +0200 | [diff] [blame] | 81 | pnp_exit_conf_state(dev); |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 82 | } |
| 83 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 84 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 85 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 86 | struct pei_data pei_data_template = { |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 87 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 88 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 89 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 90 | .epbar = DEFAULT_EPBAR, |
| 91 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 92 | .smbusbar = SMBUS_IO_BASE, |
| 93 | .wdbbar = 0x4000000, |
| 94 | .wdbsize = 0x1000, |
| 95 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 96 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 97 | .pmbase = DEFAULT_PMBASE, |
| 98 | .gpiobase = DEFAULT_GPIOBASE, |
| 99 | .thermalbase = 0xfed08000, |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 100 | .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 101 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 102 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 103 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 104 | .ec_present = 1, |
| 105 | .gbe_enable = 1, |
| 106 | .ddr3lv_support = 0, |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 107 | /* |
| 108 | * 0 = leave channel enabled |
| 109 | * 1 = disable dimm 0 on channel |
| 110 | * 2 = disable dimm 1 on channel |
| 111 | * 3 = disable dimm 0+1 on channel |
| 112 | */ |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 113 | .dimm_channel0_disabled = 2, |
| 114 | .dimm_channel1_disabled = 2, |
| 115 | .max_ddr3_freq = 1600, |
| 116 | .usb_port_config = { |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 117 | /* enabled usb oc pin length */ |
| 118 | { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ |
| 119 | { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ |
| 120 | { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ |
| 121 | { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */ |
| 122 | { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */ |
| 123 | { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */ |
| 124 | { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */ |
| 125 | { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */ |
| 126 | { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */ |
| 127 | { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */ |
| 128 | { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */ |
| 129 | { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */ |
| 130 | { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */ |
| 131 | { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */ |
| 132 | }, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 133 | .usb3 = { |
| 134 | .mode = 3, /* Smart Auto? */ |
| 135 | .hs_port_switch_mask = 0xf, /* All four ports. */ |
| 136 | .preboot_support = 1, /* preOS driver? */ |
| 137 | .xhci_streams = 1, /* Enable. */ |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 138 | }, |
Edward O'Callaghan | 6f49f69 | 2014-05-24 02:04:52 +1000 | [diff] [blame] | 139 | .pcie_init = 1, |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 140 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 141 | *pei_data = pei_data_template; |
| 142 | } |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 143 | |
Vladimir Serbinenko | a50478f | 2016-02-10 03:03:41 +0100 | [diff] [blame] | 144 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 145 | /* enabled power usb oc pin */ |
| 146 | { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ |
| 147 | { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ |
| 148 | { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ |
| 149 | { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */ |
| 150 | { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */ |
| 151 | { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */ |
| 152 | { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */ |
| 153 | { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */ |
| 154 | { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */ |
| 155 | { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */ |
| 156 | { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */ |
| 157 | { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */ |
| 158 | { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */ |
| 159 | { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ |
| 160 | }; |
| 161 | |
Peter Lemenkov | 498f1cc | 2019-02-07 10:48:10 +0100 | [diff] [blame] | 162 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 163 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 164 | read_spd(&spd[0], 0x50, id_only); |
| 165 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | a50478f | 2016-02-10 03:03:41 +0100 | [diff] [blame] | 166 | } |
| 167 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 168 | void mainboard_early_init(int s3resume) |
| 169 | { |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 170 | /* Enable PEG10 (1x16) */ |
| 171 | pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, |
| 172 | pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | |
| 173 | DEVEN_PEG10); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 174 | } |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 175 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 176 | int mainboard_should_reset_usb(int s3resume) |
| 177 | { |
| 178 | return !s3resume; |
Nico Huber | efe1fed | 2013-04-29 18:00:57 +0200 | [diff] [blame] | 179 | } |