Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Elyes HAOUAS | c4d1b47 | 2021-01-31 08:26:01 +0100 | [diff] [blame] | 4 | #include <arch/pci_io_cfg.h> |
Angel Pons | 1ac6f8b | 2021-01-20 13:13:26 +0100 | [diff] [blame] | 5 | #include <assert.h> |
Angel Pons | 1ac6f8b | 2021-01-20 13:13:26 +0100 | [diff] [blame] | 6 | #include <types.h> |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 7 | |
Jacob Garber | 4a21647 | 2019-12-27 14:18:32 -0700 | [diff] [blame] | 8 | #include "gm45.h" |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 9 | |
Angel Pons | 1ac6f8b | 2021-01-20 13:13:26 +0100 | [diff] [blame] | 10 | static uint32_t encode_pciexbar_length(void) |
| 11 | { |
| 12 | switch (CONFIG_MMCONF_BUS_NUMBER) { |
| 13 | case 256: return 0 << 1; |
| 14 | case 128: return 1 << 1; |
| 15 | case 64: return 2 << 1; |
| 16 | default: return dead_code_t(uint32_t); |
| 17 | } |
| 18 | } |
| 19 | |
Arthur Heymans | be9533a | 2019-10-12 14:35:25 +0200 | [diff] [blame] | 20 | void bootblock_early_northbridge_init(void) |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 21 | { |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 22 | /* |
| 23 | * The "io" variant of the config access is explicitly used to |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 24 | * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to |
Elyes HAOUAS | 4537332 | 2021-01-16 15:01:43 +0100 | [diff] [blame] | 25 | * true. That way all subsequent non-explicit config accesses use |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 26 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 27 | * the first thing called in the non-asm boot block code. The final |
| 28 | * assumption is that no assembly code is using the |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 29 | * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 30 | * |
| 31 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 32 | * 4GiB. |
| 33 | */ |
Elyes HAOUAS | c4d1b47 | 2021-01-31 08:26:01 +0100 | [diff] [blame] | 34 | const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; |
Angel Pons | 1ac6f8b | 2021-01-20 13:13:26 +0100 | [diff] [blame] | 35 | pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); |
Elyes HAOUAS | c4d1b47 | 2021-01-31 08:26:01 +0100 | [diff] [blame] | 36 | pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 37 | } |