Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 4 | #include <acpi/acpi_gnvs.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpigen.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 6 | #include <arch/smp/mpspec.h> |
| 7 | #include <cbmem.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 9 | #include <cpu/x86/smm.h> |
| 10 | #include <console/console.h> |
| 11 | #include <types.h> |
| 12 | #include <string.h> |
| 13 | #include <arch/cpu.h> |
| 14 | #include <cpu/x86/msr.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | #include <cpu/intel/turbo.h> |
| 16 | #include <ec/google/chromeec/ec.h> |
| 17 | #include <vendorcode/google/chromeos/gnvs.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 18 | #include <soc/acpi.h> |
| 19 | #include <soc/cpu.h> |
| 20 | #include <soc/iomap.h> |
| 21 | #include <soc/lpc.h> |
| 22 | #include <soc/msr.h> |
| 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/pm.h> |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 25 | #include <soc/systemagent.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 26 | #include <soc/intel/broadwell/chip.h> |
Sumeet R Pawnikar | fa42d56 | 2020-05-08 22:18:09 +0530 | [diff] [blame] | 27 | #include <intelblocks/cpulib.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 28 | |
| 29 | /* |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 30 | * List of supported C-states in this processor. Only the ULT parts support C8, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 31 | * C9, and C10. |
| 32 | */ |
| 33 | enum { |
| 34 | C_STATE_C0, /* 0 */ |
| 35 | C_STATE_C1, /* 1 */ |
| 36 | C_STATE_C1E, /* 2 */ |
| 37 | C_STATE_C3, /* 3 */ |
| 38 | C_STATE_C6_SHORT_LAT, /* 4 */ |
| 39 | C_STATE_C6_LONG_LAT, /* 5 */ |
| 40 | C_STATE_C7_SHORT_LAT, /* 6 */ |
| 41 | C_STATE_C7_LONG_LAT, /* 7 */ |
| 42 | C_STATE_C7S_SHORT_LAT, /* 8 */ |
| 43 | C_STATE_C7S_LONG_LAT, /* 9 */ |
| 44 | C_STATE_C8, /* 10 */ |
| 45 | C_STATE_C9, /* 11 */ |
| 46 | C_STATE_C10, /* 12 */ |
| 47 | NUM_C_STATES |
| 48 | }; |
| 49 | |
| 50 | #define MWAIT_RES(state, sub_state) \ |
| 51 | { \ |
| 52 | .addrl = (((state) << 4) | (sub_state)), \ |
| 53 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 54 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 55 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 56 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 57 | } |
| 58 | |
| 59 | static acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 60 | [C_STATE_C0] = { }, |
| 61 | [C_STATE_C1] = { |
| 62 | .latency = 0, |
| 63 | .power = 1000, |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 64 | .resource = MWAIT_RES(0, 0), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 65 | }, |
| 66 | [C_STATE_C1E] = { |
| 67 | .latency = 0, |
| 68 | .power = 1000, |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 69 | .resource = MWAIT_RES(0, 1), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 70 | }, |
| 71 | [C_STATE_C3] = { |
| 72 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 73 | .power = 900, |
| 74 | .resource = MWAIT_RES(1, 0), |
| 75 | }, |
| 76 | [C_STATE_C6_SHORT_LAT] = { |
| 77 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 78 | .power = 800, |
| 79 | .resource = MWAIT_RES(2, 0), |
| 80 | }, |
| 81 | [C_STATE_C6_LONG_LAT] = { |
| 82 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 83 | .power = 800, |
| 84 | .resource = MWAIT_RES(2, 1), |
| 85 | }, |
| 86 | [C_STATE_C7_SHORT_LAT] = { |
| 87 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 88 | .power = 700, |
| 89 | .resource = MWAIT_RES(3, 0), |
| 90 | }, |
| 91 | [C_STATE_C7_LONG_LAT] = { |
| 92 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 93 | .power = 700, |
| 94 | .resource = MWAIT_RES(3, 1), |
| 95 | }, |
| 96 | [C_STATE_C7S_SHORT_LAT] = { |
| 97 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 98 | .power = 700, |
| 99 | .resource = MWAIT_RES(3, 2), |
| 100 | }, |
| 101 | [C_STATE_C7S_LONG_LAT] = { |
| 102 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 103 | .power = 700, |
| 104 | .resource = MWAIT_RES(3, 3), |
| 105 | }, |
| 106 | [C_STATE_C8] = { |
| 107 | .latency = C_STATE_LATENCY_FROM_LAT_REG(3), |
| 108 | .power = 600, |
| 109 | .resource = MWAIT_RES(4, 0), |
| 110 | }, |
| 111 | [C_STATE_C9] = { |
| 112 | .latency = C_STATE_LATENCY_FROM_LAT_REG(4), |
| 113 | .power = 500, |
| 114 | .resource = MWAIT_RES(5, 0), |
| 115 | }, |
| 116 | [C_STATE_C10] = { |
| 117 | .latency = C_STATE_LATENCY_FROM_LAT_REG(5), |
| 118 | .power = 400, |
| 119 | .resource = MWAIT_RES(6, 0), |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | static int cstate_set_s0ix[3] = { |
| 124 | C_STATE_C1E, |
| 125 | C_STATE_C7S_LONG_LAT, |
| 126 | C_STATE_C10 |
| 127 | }; |
| 128 | |
| 129 | static int cstate_set_non_s0ix[3] = { |
| 130 | C_STATE_C1E, |
| 131 | C_STATE_C3, |
| 132 | C_STATE_C7S_LONG_LAT |
| 133 | }; |
| 134 | |
| 135 | static int get_cores_per_package(void) |
| 136 | { |
| 137 | struct cpuinfo_x86 c; |
| 138 | struct cpuid_result result; |
| 139 | int cores = 1; |
| 140 | |
| 141 | get_fms(&c, cpuid_eax(1)); |
| 142 | if (c.x86 != 6) |
| 143 | return 1; |
| 144 | |
| 145 | result = cpuid_ext(0xb, 1); |
| 146 | cores = result.ebx & 0xff; |
| 147 | |
| 148 | return cores; |
| 149 | } |
| 150 | |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 151 | void acpi_init_gnvs(struct global_nvs *gnvs) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 152 | { |
| 153 | /* Set unknown wake source */ |
| 154 | gnvs->pm1i = -1; |
| 155 | |
| 156 | /* CPU core count */ |
| 157 | gnvs->pcnt = dev_count_cpu(); |
| 158 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 159 | #if CONFIG(CONSOLE_CBMEM) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 160 | /* Update the mem console pointer. */ |
| 161 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 162 | #endif |
| 163 | |
Kyösti Mälkki | 000d91a | 2020-06-15 13:04:48 +0300 | [diff] [blame] | 164 | if (CONFIG(CHROMEOS)) { |
| 165 | /* Initialize Verified Boot data */ |
| 166 | chromeos_init_chromeos_acpi(&(gnvs->chromeos)); |
| 167 | if (CONFIG(EC_GOOGLE_CHROMEEC)) { |
| 168 | gnvs->chromeos.vbt2 = google_ec_running_ro() ? |
| 169 | ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; |
| 170 | } else { |
| 171 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 172 | } |
| 173 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 174 | } |
| 175 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 176 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 177 | { |
| 178 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 179 | MCFG_BASE_ADDRESS, 0, 0, 255); |
| 180 | return current; |
| 181 | } |
| 182 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 183 | static acpi_tstate_t tss_table_fine[] = { |
| 184 | { 100, 1000, 0, 0x00, 0 }, |
| 185 | { 94, 940, 0, 0x1f, 0 }, |
| 186 | { 88, 880, 0, 0x1e, 0 }, |
| 187 | { 82, 820, 0, 0x1d, 0 }, |
| 188 | { 75, 760, 0, 0x1c, 0 }, |
| 189 | { 69, 700, 0, 0x1b, 0 }, |
| 190 | { 63, 640, 0, 0x1a, 0 }, |
| 191 | { 57, 580, 0, 0x19, 0 }, |
| 192 | { 50, 520, 0, 0x18, 0 }, |
| 193 | { 44, 460, 0, 0x17, 0 }, |
| 194 | { 38, 400, 0, 0x16, 0 }, |
| 195 | { 32, 340, 0, 0x15, 0 }, |
| 196 | { 25, 280, 0, 0x14, 0 }, |
| 197 | { 19, 220, 0, 0x13, 0 }, |
| 198 | { 13, 160, 0, 0x12, 0 }, |
| 199 | }; |
| 200 | |
| 201 | static acpi_tstate_t tss_table_coarse[] = { |
| 202 | { 100, 1000, 0, 0x00, 0 }, |
| 203 | { 88, 875, 0, 0x1f, 0 }, |
| 204 | { 75, 750, 0, 0x1e, 0 }, |
| 205 | { 63, 625, 0, 0x1d, 0 }, |
| 206 | { 50, 500, 0, 0x1c, 0 }, |
| 207 | { 38, 375, 0, 0x1b, 0 }, |
| 208 | { 25, 250, 0, 0x1a, 0 }, |
| 209 | { 13, 125, 0, 0x19, 0 }, |
| 210 | }; |
| 211 | |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 212 | static void generate_T_state_entries(int core, int cores_per_package) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 213 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 214 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 215 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 216 | |
| 217 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 218 | acpigen_write_empty_PTC(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 219 | |
| 220 | /* Set a T-state limit that can be modified in NVS */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 221 | acpigen_write_TPC("\\TLVL"); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 222 | |
| 223 | /* |
| 224 | * CPUID.(EAX=6):EAX[5] indicates support |
| 225 | * for extended throttle levels. |
| 226 | */ |
| 227 | if (cpuid_eax(6) & (1 << 5)) |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 228 | acpigen_write_TSS_package( |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 229 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 230 | else |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 231 | acpigen_write_TSS_package( |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 232 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 233 | } |
| 234 | |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 235 | static void generate_C_state_entries(void) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 236 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 237 | acpi_cstate_t map[3]; |
| 238 | int *set; |
| 239 | int i; |
| 240 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 241 | config_t *config = config_of_soc(); |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 242 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 243 | if (config->s0ix_enable) |
| 244 | set = cstate_set_s0ix; |
| 245 | else |
| 246 | set = cstate_set_non_s0ix; |
| 247 | |
| 248 | for (i = 0; i < 3; i++) { |
| 249 | memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); |
| 250 | map[i].ctype = i + 1; |
| 251 | } |
| 252 | |
| 253 | /* Generate C-state tables */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 254 | acpigen_write_CST_package(map, ARRAY_SIZE(map)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 258 | { |
| 259 | u32 m; |
| 260 | u32 power; |
| 261 | |
| 262 | /* |
| 263 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 264 | * |
| 265 | * Power = (ratio / p1_ratio) * m * tdp |
| 266 | */ |
| 267 | |
| 268 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 269 | m = (m * m) / 1000; |
| 270 | |
| 271 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 272 | power *= (m / 100) * (tdp / 1000); |
| 273 | power /= 1000; |
| 274 | |
| 275 | return (int)power; |
| 276 | } |
| 277 | |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 278 | static void generate_P_state_entries(int core, int cores_per_package) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 279 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 280 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 281 | int coord_type, power_max, power_unit, num_entries; |
| 282 | int ratio, power, clock, clock_max; |
| 283 | msr_t msr; |
| 284 | |
| 285 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 286 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 287 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 288 | coord_type = SW_ANY; |
| 289 | else |
| 290 | coord_type = HW_ALL; |
| 291 | |
| 292 | /* Get bus ratio limits and calculate clock speeds */ |
| 293 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 294 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 295 | |
| 296 | /* Determine if this CPU has configurable TDP */ |
| 297 | if (cpu_config_tdp_levels()) { |
| 298 | /* Set max ratio to nominal TDP ratio */ |
| 299 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 300 | ratio_max = msr.lo & 0xff; |
| 301 | } else { |
| 302 | /* Max Non-Turbo Ratio */ |
| 303 | ratio_max = (msr.lo >> 8) & 0xff; |
| 304 | } |
| 305 | clock_max = ratio_max * CPU_BCLK; |
| 306 | |
| 307 | /* Calculate CPU TDP in mW */ |
| 308 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 309 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 310 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 311 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 312 | |
| 313 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 314 | acpigen_write_empty_PCT(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 315 | |
| 316 | /* Write _PPC with no limit on supported P-state */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 317 | acpigen_write_PPC_NVS(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 318 | |
| 319 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 320 | acpigen_write_PSD_package(core, 1, coord_type); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 321 | |
| 322 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 323 | acpigen_write_name("_PSS"); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 324 | |
| 325 | /* Determine ratio points */ |
| 326 | ratio_step = PSS_RATIO_STEP; |
| 327 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 328 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 329 | ratio_step <<= 1; |
| 330 | num_entries >>= 1; |
| 331 | } |
| 332 | |
| 333 | /* P[T] is Turbo state if enabled */ |
| 334 | if (get_turbo_state() == TURBO_ENABLED) { |
| 335 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 336 | acpigen_write_package(num_entries + 2); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 337 | |
| 338 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 339 | ratio_turbo = msr.lo & 0xff; |
| 340 | |
| 341 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 342 | acpigen_write_PSS_package( |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 343 | clock_max + 1, /*MHz*/ |
| 344 | power_max, /*mW*/ |
| 345 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 346 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 347 | ratio_turbo << 8, /*control*/ |
| 348 | ratio_turbo << 8); /*status*/ |
| 349 | } else { |
| 350 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 351 | acpigen_write_package(num_entries + 1); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | /* First regular entry is max non-turbo ratio */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 355 | acpigen_write_PSS_package( |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 356 | clock_max, /*MHz*/ |
| 357 | power_max, /*mW*/ |
| 358 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 359 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 360 | ratio_max << 8, /*control*/ |
| 361 | ratio_max << 8); /*status*/ |
| 362 | |
| 363 | /* Generate the remaining entries */ |
| 364 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 365 | ratio >= ratio_min; ratio -= ratio_step) { |
| 366 | |
| 367 | /* Calculate power at this ratio */ |
| 368 | power = calculate_power(power_max, ratio_max, ratio); |
| 369 | clock = ratio * CPU_BCLK; |
| 370 | |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 371 | acpigen_write_PSS_package( |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 372 | clock, /*MHz*/ |
| 373 | power, /*mW*/ |
| 374 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 375 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 376 | ratio << 8, /*control*/ |
| 377 | ratio << 8); /*status*/ |
| 378 | } |
| 379 | |
| 380 | /* Fix package length */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 381 | acpigen_pop_len(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 382 | } |
| 383 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 384 | void generate_cpu_entries(const struct device *device) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 385 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 386 | int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; |
| 387 | int totalcores = dev_count_cpu(); |
| 388 | int cores_per_package = get_cores_per_package(); |
| 389 | int numcpus = totalcores/cores_per_package; |
| 390 | |
| 391 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 392 | numcpus, cores_per_package); |
| 393 | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 394 | for (cpuID = 1; cpuID <= numcpus; cpuID++) { |
| 395 | for (coreID = 1; coreID <= cores_per_package; coreID++) { |
| 396 | if (coreID > 1) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 397 | pcontrol_blk = 0; |
| 398 | plen = 0; |
| 399 | } |
| 400 | |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 401 | /* Generate processor \_SB.CPUx */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 402 | acpigen_write_processor( |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 403 | (cpuID - 1) * cores_per_package+coreID - 1, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 404 | pcontrol_blk, plen); |
| 405 | |
| 406 | /* Generate P-state tables */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 407 | generate_P_state_entries( |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 408 | coreID - 1, cores_per_package); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 409 | |
| 410 | /* Generate C-state tables */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 411 | generate_C_state_entries(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 412 | |
| 413 | /* Generate T-state tables */ |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 414 | generate_T_state_entries( |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 415 | cpuID - 1, cores_per_package); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 416 | |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 417 | acpigen_pop_len(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 418 | } |
| 419 | } |
Arthur Heymans | f7d1c8d | 2018-11-28 12:22:59 +0100 | [diff] [blame] | 420 | |
| 421 | /* PPKG is usually used for thermal management |
| 422 | of the first and only package. */ |
| 423 | acpigen_write_processor_package("PPKG", 0, cores_per_package); |
| 424 | |
| 425 | /* Add a method to notify processor nodes */ |
| 426 | acpigen_write_processor_cnot(cores_per_package); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 427 | } |
| 428 | |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 429 | static unsigned long acpi_fill_dmar(unsigned long current) |
| 430 | { |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 431 | struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 432 | const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; |
| 433 | const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; |
| 434 | const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; |
| 435 | const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; |
| 436 | |
| 437 | /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ |
Angel Pons | 37799b3 | 2020-08-03 12:17:22 +0200 | [diff] [blame^] | 438 | const bool emit_igd = |
| 439 | igfx_dev && igfx_dev->enabled && |
| 440 | gfxvtbar && gfxvten && |
| 441 | !MCHBAR32(GFXVTBAR + 4); |
| 442 | |
| 443 | /* First, add DRHD entries */ |
| 444 | if (emit_igd) { |
| 445 | const unsigned long tmp = current; |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 446 | |
| 447 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
Matt DeVillier | 7866d49 | 2018-03-29 14:59:57 +0200 | [diff] [blame] | 448 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 449 | |
| 450 | acpi_dmar_drhd_fixup(tmp, current); |
| 451 | } |
| 452 | |
| 453 | /* VTVC0BAR has to be set, enabled, and in 32-bit space */ |
| 454 | if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { |
| 455 | const unsigned long tmp = current; |
| 456 | current += acpi_create_dmar_drhd(current, |
| 457 | DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
Matt DeVillier | 7866d49 | 2018-03-29 14:59:57 +0200 | [diff] [blame] | 458 | current += acpi_create_dmar_ds_ioapic(current, |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 459 | 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); |
| 460 | size_t i; |
| 461 | for (i = 0; i < 8; ++i) |
Matt DeVillier | 7866d49 | 2018-03-29 14:59:57 +0200 | [diff] [blame] | 462 | current += acpi_create_dmar_ds_msi_hpet(current, |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 463 | 0, PCH_HPET_PCI_BUS, |
| 464 | PCH_HPET_PCI_SLOT, i); |
| 465 | acpi_dmar_drhd_fixup(tmp, current); |
| 466 | } |
| 467 | |
Angel Pons | 37799b3 | 2020-08-03 12:17:22 +0200 | [diff] [blame^] | 468 | /* Then, add RMRR entries after all DRHD entries */ |
| 469 | if (emit_igd) { |
| 470 | const unsigned long tmp = current; |
| 471 | |
| 472 | current += acpi_create_dmar_rmrr(current, 0, |
| 473 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 474 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 475 | acpi_dmar_rmrr_fixup(tmp, current); |
| 476 | } |
| 477 | |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 478 | return current; |
| 479 | } |
| 480 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 481 | unsigned long northbridge_write_acpi_tables(const struct device *const dev, |
Matt DeVillier | 0f49bbc | 2018-02-19 17:35:55 -0600 | [diff] [blame] | 482 | unsigned long current, |
| 483 | struct acpi_rsdp *const rsdp) |
| 484 | { |
| 485 | /* Create DMAR table only if we have VT-d capability. */ |
| 486 | const u32 capid0_a = pci_read_config32(dev, CAPID0_A); |
| 487 | if (capid0_a & VTD_DISABLE) |
| 488 | return current; |
| 489 | |
| 490 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 491 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 492 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); |
| 493 | current += dmar->header.length; |
| 494 | current = acpi_align_current(current); |
| 495 | acpi_add_table(rsdp, dmar); |
| 496 | |
| 497 | return current; |
| 498 | } |
| 499 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 500 | unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 501 | { |
| 502 | int sci = acpi_sci_irq(); |
| 503 | acpi_madt_irqoverride_t *irqovr; |
| 504 | uint16_t flags = MP_IRQ_TRIGGER_LEVEL; |
| 505 | |
| 506 | /* INT_SRC_OVR */ |
| 507 | irqovr = (void *)current; |
| 508 | current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); |
| 509 | |
| 510 | if (sci >= 20) |
| 511 | flags |= MP_IRQ_POLARITY_LOW; |
| 512 | else |
| 513 | flags |= MP_IRQ_POLARITY_HIGH; |
| 514 | |
| 515 | /* SCI */ |
| 516 | irqovr = (void *)current; |
| 517 | current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); |
| 518 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 519 | return current; |
| 520 | } |