Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/acpi.h> |
| 22 | #include <arch/acpigen.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <arch/smp/mpspec.h> |
| 25 | #include <cbmem.h> |
| 26 | #include <console/console.h> |
| 27 | #include <cpu/x86/smm.h> |
| 28 | #include <console/console.h> |
| 29 | #include <types.h> |
| 30 | #include <string.h> |
| 31 | #include <arch/cpu.h> |
| 32 | #include <cpu/x86/msr.h> |
| 33 | #include <cpu/x86/tsc.h> |
| 34 | #include <cpu/intel/turbo.h> |
| 35 | #include <ec/google/chromeec/ec.h> |
| 36 | #include <vendorcode/google/chromeos/gnvs.h> |
| 37 | #include <broadwell/acpi.h> |
| 38 | #include <broadwell/cpu.h> |
| 39 | #include <broadwell/iomap.h> |
| 40 | #include <broadwell/lpc.h> |
| 41 | #include <broadwell/msr.h> |
| 42 | #include <broadwell/pci_devs.h> |
| 43 | #include <broadwell/pm.h> |
| 44 | #include <chip.h> |
| 45 | |
| 46 | /* |
| 47 | * List of suported C-states in this processor. Only the ULT parts support C8, |
| 48 | * C9, and C10. |
| 49 | */ |
| 50 | enum { |
| 51 | C_STATE_C0, /* 0 */ |
| 52 | C_STATE_C1, /* 1 */ |
| 53 | C_STATE_C1E, /* 2 */ |
| 54 | C_STATE_C3, /* 3 */ |
| 55 | C_STATE_C6_SHORT_LAT, /* 4 */ |
| 56 | C_STATE_C6_LONG_LAT, /* 5 */ |
| 57 | C_STATE_C7_SHORT_LAT, /* 6 */ |
| 58 | C_STATE_C7_LONG_LAT, /* 7 */ |
| 59 | C_STATE_C7S_SHORT_LAT, /* 8 */ |
| 60 | C_STATE_C7S_LONG_LAT, /* 9 */ |
| 61 | C_STATE_C8, /* 10 */ |
| 62 | C_STATE_C9, /* 11 */ |
| 63 | C_STATE_C10, /* 12 */ |
| 64 | NUM_C_STATES |
| 65 | }; |
| 66 | |
| 67 | #define MWAIT_RES(state, sub_state) \ |
| 68 | { \ |
| 69 | .addrl = (((state) << 4) | (sub_state)), \ |
| 70 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 71 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 72 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 73 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 74 | } |
| 75 | |
| 76 | static acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 77 | [C_STATE_C0] = { }, |
| 78 | [C_STATE_C1] = { |
| 79 | .latency = 0, |
| 80 | .power = 1000, |
| 81 | .resource = MWAIT_RES(0,0), |
| 82 | }, |
| 83 | [C_STATE_C1E] = { |
| 84 | .latency = 0, |
| 85 | .power = 1000, |
| 86 | .resource = MWAIT_RES(0,1), |
| 87 | }, |
| 88 | [C_STATE_C3] = { |
| 89 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 90 | .power = 900, |
| 91 | .resource = MWAIT_RES(1, 0), |
| 92 | }, |
| 93 | [C_STATE_C6_SHORT_LAT] = { |
| 94 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 95 | .power = 800, |
| 96 | .resource = MWAIT_RES(2, 0), |
| 97 | }, |
| 98 | [C_STATE_C6_LONG_LAT] = { |
| 99 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 100 | .power = 800, |
| 101 | .resource = MWAIT_RES(2, 1), |
| 102 | }, |
| 103 | [C_STATE_C7_SHORT_LAT] = { |
| 104 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 105 | .power = 700, |
| 106 | .resource = MWAIT_RES(3, 0), |
| 107 | }, |
| 108 | [C_STATE_C7_LONG_LAT] = { |
| 109 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 110 | .power = 700, |
| 111 | .resource = MWAIT_RES(3, 1), |
| 112 | }, |
| 113 | [C_STATE_C7S_SHORT_LAT] = { |
| 114 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 115 | .power = 700, |
| 116 | .resource = MWAIT_RES(3, 2), |
| 117 | }, |
| 118 | [C_STATE_C7S_LONG_LAT] = { |
| 119 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 120 | .power = 700, |
| 121 | .resource = MWAIT_RES(3, 3), |
| 122 | }, |
| 123 | [C_STATE_C8] = { |
| 124 | .latency = C_STATE_LATENCY_FROM_LAT_REG(3), |
| 125 | .power = 600, |
| 126 | .resource = MWAIT_RES(4, 0), |
| 127 | }, |
| 128 | [C_STATE_C9] = { |
| 129 | .latency = C_STATE_LATENCY_FROM_LAT_REG(4), |
| 130 | .power = 500, |
| 131 | .resource = MWAIT_RES(5, 0), |
| 132 | }, |
| 133 | [C_STATE_C10] = { |
| 134 | .latency = C_STATE_LATENCY_FROM_LAT_REG(5), |
| 135 | .power = 400, |
| 136 | .resource = MWAIT_RES(6, 0), |
| 137 | }, |
| 138 | }; |
| 139 | |
| 140 | static int cstate_set_s0ix[3] = { |
| 141 | C_STATE_C1E, |
| 142 | C_STATE_C7S_LONG_LAT, |
| 143 | C_STATE_C10 |
| 144 | }; |
| 145 | |
| 146 | static int cstate_set_non_s0ix[3] = { |
| 147 | C_STATE_C1E, |
| 148 | C_STATE_C3, |
| 149 | C_STATE_C7S_LONG_LAT |
| 150 | }; |
| 151 | |
| 152 | static int get_cores_per_package(void) |
| 153 | { |
| 154 | struct cpuinfo_x86 c; |
| 155 | struct cpuid_result result; |
| 156 | int cores = 1; |
| 157 | |
| 158 | get_fms(&c, cpuid_eax(1)); |
| 159 | if (c.x86 != 6) |
| 160 | return 1; |
| 161 | |
| 162 | result = cpuid_ext(0xb, 1); |
| 163 | cores = result.ebx & 0xff; |
| 164 | |
| 165 | return cores; |
| 166 | } |
| 167 | |
| 168 | void acpi_init_gnvs(global_nvs_t *gnvs) |
| 169 | { |
| 170 | /* Set unknown wake source */ |
| 171 | gnvs->pm1i = -1; |
| 172 | |
| 173 | /* CPU core count */ |
| 174 | gnvs->pcnt = dev_count_cpu(); |
| 175 | |
| 176 | #if CONFIG_CONSOLE_CBMEM |
| 177 | /* Update the mem console pointer. */ |
| 178 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 179 | #endif |
| 180 | |
| 181 | #if CONFIG_CHROMEOS |
| 182 | /* Initialize Verified Boot data */ |
| 183 | chromeos_init_vboot(&(gnvs->chromeos)); |
| 184 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 185 | gnvs->chromeos.vbt2 = google_ec_running_ro() ? |
| 186 | ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; |
| 187 | #endif |
| 188 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 189 | #endif |
| 190 | } |
| 191 | |
| 192 | void acpi_create_intel_hpet(acpi_hpet_t * hpet) |
| 193 | { |
| 194 | acpi_header_t *header = &(hpet->header); |
| 195 | acpi_addr_t *addr = &(hpet->addr); |
| 196 | |
| 197 | memset((void *) hpet, 0, sizeof(acpi_hpet_t)); |
| 198 | |
| 199 | /* fill out header fields */ |
| 200 | memcpy(header->signature, "HPET", 4); |
| 201 | memcpy(header->oem_id, OEM_ID, 6); |
| 202 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 203 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 204 | |
| 205 | header->length = sizeof(acpi_hpet_t); |
| 206 | header->revision = 1; |
| 207 | |
| 208 | /* fill out HPET address */ |
| 209 | addr->space_id = 0; /* Memory */ |
| 210 | addr->bit_width = 64; |
| 211 | addr->bit_offset = 0; |
| 212 | addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; |
| 213 | addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; |
| 214 | |
| 215 | hpet->id = 0x8086a201; /* Intel */ |
| 216 | hpet->number = 0x00; |
| 217 | hpet->min_tick = 0x0080; |
| 218 | |
| 219 | header->checksum = |
| 220 | acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); |
| 221 | } |
| 222 | |
| 223 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 224 | { |
| 225 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 226 | MCFG_BASE_ADDRESS, 0, 0, 255); |
| 227 | return current; |
| 228 | } |
| 229 | |
| 230 | void acpi_fill_in_fadt(acpi_fadt_t *fadt) |
| 231 | { |
| 232 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 233 | |
| 234 | fadt->sci_int = acpi_sci_irq(); |
| 235 | fadt->smi_cmd = APM_CNT; |
| 236 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 237 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 238 | fadt->s4bios_req = 0x0; |
| 239 | fadt->pstate_cnt = 0; |
| 240 | |
| 241 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 242 | fadt->pm1b_evt_blk = 0x0; |
| 243 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 244 | fadt->pm1b_cnt_blk = 0x0; |
| 245 | fadt->pm2_cnt_blk = pmbase + PM2_CNT; |
| 246 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 247 | fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| 248 | fadt->gpe1_blk = 0; |
| 249 | |
| 250 | fadt->pm1_evt_len = 4; |
| 251 | fadt->pm1_cnt_len = 2; |
| 252 | fadt->pm2_cnt_len = 1; |
| 253 | fadt->pm_tmr_len = 4; |
| 254 | fadt->gpe0_blk_len = 32; |
| 255 | fadt->gpe1_blk_len = 0; |
| 256 | fadt->gpe1_base = 0; |
| 257 | fadt->cst_cnt = 0; |
| 258 | fadt->p_lvl2_lat = 1; |
| 259 | fadt->p_lvl3_lat = 87; |
| 260 | fadt->flush_size = 1024; |
| 261 | fadt->flush_stride = 16; |
| 262 | fadt->duty_offset = 1; |
| 263 | fadt->duty_width = 0; |
| 264 | fadt->day_alrm = 0xd; |
| 265 | fadt->mon_alrm = 0x00; |
| 266 | fadt->century = 0x00; |
| 267 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 268 | |
| 269 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 270 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 271 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | |
| 272 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 273 | |
| 274 | fadt->reset_reg.space_id = 1; |
| 275 | fadt->reset_reg.bit_width = 8; |
| 276 | fadt->reset_reg.bit_offset = 0; |
| 277 | fadt->reset_reg.resv = 0; |
| 278 | fadt->reset_reg.addrl = 0xcf9; |
| 279 | fadt->reset_reg.addrh = 0; |
| 280 | fadt->reset_value = 6; |
| 281 | |
| 282 | fadt->x_pm1a_evt_blk.space_id = 1; |
| 283 | fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
| 284 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 285 | fadt->x_pm1a_evt_blk.resv = 0; |
| 286 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| 287 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 288 | |
| 289 | fadt->x_pm1b_evt_blk.space_id = 1; |
| 290 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 291 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 292 | fadt->x_pm1b_evt_blk.resv = 0; |
| 293 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 294 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 295 | |
| 296 | fadt->x_pm1a_cnt_blk.space_id = 1; |
| 297 | fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
| 298 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 299 | fadt->x_pm1a_cnt_blk.resv = 0; |
| 300 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| 301 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 302 | |
| 303 | fadt->x_pm1b_cnt_blk.space_id = 1; |
| 304 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 305 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 306 | fadt->x_pm1b_cnt_blk.resv = 0; |
| 307 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 308 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 309 | |
| 310 | fadt->x_pm2_cnt_blk.space_id = 1; |
| 311 | fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; |
| 312 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 313 | fadt->x_pm2_cnt_blk.resv = 0; |
| 314 | fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; |
| 315 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 316 | |
| 317 | fadt->x_pm_tmr_blk.space_id = 1; |
| 318 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 319 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 320 | fadt->x_pm_tmr_blk.resv = 0; |
| 321 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 322 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 323 | |
| 324 | fadt->x_gpe0_blk.space_id = 0; |
| 325 | fadt->x_gpe0_blk.bit_width = 0; |
| 326 | fadt->x_gpe0_blk.bit_offset = 0; |
| 327 | fadt->x_gpe0_blk.resv = 0; |
| 328 | fadt->x_gpe0_blk.addrl = 0; |
| 329 | fadt->x_gpe0_blk.addrh = 0; |
| 330 | |
| 331 | fadt->x_gpe1_blk.space_id = 1; |
| 332 | fadt->x_gpe1_blk.bit_width = 0; |
| 333 | fadt->x_gpe1_blk.bit_offset = 0; |
| 334 | fadt->x_gpe1_blk.resv = 0; |
| 335 | fadt->x_gpe1_blk.addrl = 0x0; |
| 336 | fadt->x_gpe1_blk.addrh = 0x0; |
| 337 | } |
| 338 | |
| 339 | static acpi_tstate_t tss_table_fine[] = { |
| 340 | { 100, 1000, 0, 0x00, 0 }, |
| 341 | { 94, 940, 0, 0x1f, 0 }, |
| 342 | { 88, 880, 0, 0x1e, 0 }, |
| 343 | { 82, 820, 0, 0x1d, 0 }, |
| 344 | { 75, 760, 0, 0x1c, 0 }, |
| 345 | { 69, 700, 0, 0x1b, 0 }, |
| 346 | { 63, 640, 0, 0x1a, 0 }, |
| 347 | { 57, 580, 0, 0x19, 0 }, |
| 348 | { 50, 520, 0, 0x18, 0 }, |
| 349 | { 44, 460, 0, 0x17, 0 }, |
| 350 | { 38, 400, 0, 0x16, 0 }, |
| 351 | { 32, 340, 0, 0x15, 0 }, |
| 352 | { 25, 280, 0, 0x14, 0 }, |
| 353 | { 19, 220, 0, 0x13, 0 }, |
| 354 | { 13, 160, 0, 0x12, 0 }, |
| 355 | }; |
| 356 | |
| 357 | static acpi_tstate_t tss_table_coarse[] = { |
| 358 | { 100, 1000, 0, 0x00, 0 }, |
| 359 | { 88, 875, 0, 0x1f, 0 }, |
| 360 | { 75, 750, 0, 0x1e, 0 }, |
| 361 | { 63, 625, 0, 0x1d, 0 }, |
| 362 | { 50, 500, 0, 0x1c, 0 }, |
| 363 | { 38, 375, 0, 0x1b, 0 }, |
| 364 | { 25, 250, 0, 0x1a, 0 }, |
| 365 | { 13, 125, 0, 0x19, 0 }, |
| 366 | }; |
| 367 | |
| 368 | static int generate_T_state_entries(int core, int cores_per_package) |
| 369 | { |
| 370 | int len; |
| 371 | |
| 372 | /* Indicate SW_ALL coordination for T-states */ |
| 373 | len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
| 374 | |
| 375 | /* Indicate FFixedHW so OS will use MSR */ |
| 376 | len += acpigen_write_empty_PTC(); |
| 377 | |
| 378 | /* Set a T-state limit that can be modified in NVS */ |
| 379 | len += acpigen_write_TPC("\\TLVL"); |
| 380 | |
| 381 | /* |
| 382 | * CPUID.(EAX=6):EAX[5] indicates support |
| 383 | * for extended throttle levels. |
| 384 | */ |
| 385 | if (cpuid_eax(6) & (1 << 5)) |
| 386 | len += acpigen_write_TSS_package( |
| 387 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 388 | else |
| 389 | len += acpigen_write_TSS_package( |
| 390 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
| 391 | |
| 392 | return len; |
| 393 | } |
| 394 | |
| 395 | static int generate_C_state_entries(void) |
| 396 | { |
| 397 | device_t dev = SA_DEV_ROOT; |
| 398 | config_t *config = dev->chip_info; |
| 399 | acpi_cstate_t map[3]; |
| 400 | int *set; |
| 401 | int i; |
| 402 | |
| 403 | if (config->s0ix_enable) |
| 404 | set = cstate_set_s0ix; |
| 405 | else |
| 406 | set = cstate_set_non_s0ix; |
| 407 | |
| 408 | for (i = 0; i < 3; i++) { |
| 409 | memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); |
| 410 | map[i].ctype = i + 1; |
| 411 | } |
| 412 | |
| 413 | /* Generate C-state tables */ |
| 414 | return acpigen_write_CST_package(map, ARRAY_SIZE(map)); |
| 415 | } |
| 416 | |
| 417 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 418 | { |
| 419 | u32 m; |
| 420 | u32 power; |
| 421 | |
| 422 | /* |
| 423 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 424 | * |
| 425 | * Power = (ratio / p1_ratio) * m * tdp |
| 426 | */ |
| 427 | |
| 428 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 429 | m = (m * m) / 1000; |
| 430 | |
| 431 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 432 | power *= (m / 100) * (tdp / 1000); |
| 433 | power /= 1000; |
| 434 | |
| 435 | return (int)power; |
| 436 | } |
| 437 | |
| 438 | static int generate_P_state_entries(int core, int cores_per_package) |
| 439 | { |
| 440 | int len, len_pss; |
| 441 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 442 | int coord_type, power_max, power_unit, num_entries; |
| 443 | int ratio, power, clock, clock_max; |
| 444 | msr_t msr; |
| 445 | |
| 446 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 447 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 448 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 449 | coord_type = SW_ANY; |
| 450 | else |
| 451 | coord_type = HW_ALL; |
| 452 | |
| 453 | /* Get bus ratio limits and calculate clock speeds */ |
| 454 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 455 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 456 | |
| 457 | /* Determine if this CPU has configurable TDP */ |
| 458 | if (cpu_config_tdp_levels()) { |
| 459 | /* Set max ratio to nominal TDP ratio */ |
| 460 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 461 | ratio_max = msr.lo & 0xff; |
| 462 | } else { |
| 463 | /* Max Non-Turbo Ratio */ |
| 464 | ratio_max = (msr.lo >> 8) & 0xff; |
| 465 | } |
| 466 | clock_max = ratio_max * CPU_BCLK; |
| 467 | |
| 468 | /* Calculate CPU TDP in mW */ |
| 469 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 470 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 471 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 472 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 473 | |
| 474 | /* Write _PCT indicating use of FFixedHW */ |
| 475 | len = acpigen_write_empty_PCT(); |
| 476 | |
| 477 | /* Write _PPC with no limit on supported P-state */ |
| 478 | len += acpigen_write_PPC_NVS(); |
| 479 | |
| 480 | /* Write PSD indicating configured coordination type */ |
| 481 | len += acpigen_write_PSD_package(core, 1, coord_type); |
| 482 | |
| 483 | /* Add P-state entries in _PSS table */ |
| 484 | len += acpigen_write_name("_PSS"); |
| 485 | |
| 486 | /* Determine ratio points */ |
| 487 | ratio_step = PSS_RATIO_STEP; |
| 488 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 489 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 490 | ratio_step <<= 1; |
| 491 | num_entries >>= 1; |
| 492 | } |
| 493 | |
| 494 | /* P[T] is Turbo state if enabled */ |
| 495 | if (get_turbo_state() == TURBO_ENABLED) { |
| 496 | /* _PSS package count including Turbo */ |
| 497 | len_pss = acpigen_write_package(num_entries + 2); |
| 498 | |
| 499 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 500 | ratio_turbo = msr.lo & 0xff; |
| 501 | |
| 502 | /* Add entry for Turbo ratio */ |
| 503 | len_pss += acpigen_write_PSS_package( |
| 504 | clock_max + 1, /*MHz*/ |
| 505 | power_max, /*mW*/ |
| 506 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 507 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 508 | ratio_turbo << 8, /*control*/ |
| 509 | ratio_turbo << 8); /*status*/ |
| 510 | } else { |
| 511 | /* _PSS package count without Turbo */ |
| 512 | len_pss = acpigen_write_package(num_entries + 1); |
| 513 | } |
| 514 | |
| 515 | /* First regular entry is max non-turbo ratio */ |
| 516 | len_pss += acpigen_write_PSS_package( |
| 517 | clock_max, /*MHz*/ |
| 518 | power_max, /*mW*/ |
| 519 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 520 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 521 | ratio_max << 8, /*control*/ |
| 522 | ratio_max << 8); /*status*/ |
| 523 | |
| 524 | /* Generate the remaining entries */ |
| 525 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 526 | ratio >= ratio_min; ratio -= ratio_step) { |
| 527 | |
| 528 | /* Calculate power at this ratio */ |
| 529 | power = calculate_power(power_max, ratio_max, ratio); |
| 530 | clock = ratio * CPU_BCLK; |
| 531 | |
| 532 | len_pss += acpigen_write_PSS_package( |
| 533 | clock, /*MHz*/ |
| 534 | power, /*mW*/ |
| 535 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 536 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 537 | ratio << 8, /*control*/ |
| 538 | ratio << 8); /*status*/ |
| 539 | } |
| 540 | |
| 541 | /* Fix package length */ |
| 542 | len_pss--; |
| 543 | acpigen_patch_len(len_pss); |
| 544 | |
| 545 | return len + len_pss; |
| 546 | } |
| 547 | |
| 548 | void generate_cpu_entries(void) |
| 549 | { |
| 550 | int len_pr; |
| 551 | int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; |
| 552 | int totalcores = dev_count_cpu(); |
| 553 | int cores_per_package = get_cores_per_package(); |
| 554 | int numcpus = totalcores/cores_per_package; |
| 555 | |
| 556 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 557 | numcpus, cores_per_package); |
| 558 | |
| 559 | for (cpuID=1; cpuID <=numcpus; cpuID++) { |
| 560 | for (coreID=1; coreID<=cores_per_package; coreID++) { |
| 561 | if (coreID>1) { |
| 562 | pcontrol_blk = 0; |
| 563 | plen = 0; |
| 564 | } |
| 565 | |
| 566 | /* Generate processor \_PR.CPUx */ |
| 567 | len_pr = acpigen_write_processor( |
| 568 | (cpuID-1)*cores_per_package+coreID-1, |
| 569 | pcontrol_blk, plen); |
| 570 | |
| 571 | /* Generate P-state tables */ |
| 572 | len_pr += generate_P_state_entries( |
| 573 | coreID-1, cores_per_package); |
| 574 | |
| 575 | /* Generate C-state tables */ |
| 576 | len_pr += generate_C_state_entries(); |
| 577 | |
| 578 | /* Generate T-state tables */ |
| 579 | len_pr += generate_T_state_entries( |
| 580 | cpuID-1, cores_per_package); |
| 581 | |
| 582 | len_pr--; |
| 583 | acpigen_patch_len(len_pr); |
| 584 | } |
| 585 | } |
| 586 | } |
| 587 | |
| 588 | unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 589 | { |
| 590 | int sci = acpi_sci_irq(); |
| 591 | acpi_madt_irqoverride_t *irqovr; |
| 592 | uint16_t flags = MP_IRQ_TRIGGER_LEVEL; |
| 593 | |
| 594 | /* INT_SRC_OVR */ |
| 595 | irqovr = (void *)current; |
| 596 | current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); |
| 597 | |
| 598 | if (sci >= 20) |
| 599 | flags |= MP_IRQ_POLARITY_LOW; |
| 600 | else |
| 601 | flags |= MP_IRQ_POLARITY_HIGH; |
| 602 | |
| 603 | /* SCI */ |
| 604 | irqovr = (void *)current; |
| 605 | current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); |
| 606 | |
| 607 | /* GPIO Controller */ |
| 608 | irqovr = (void *)current; |
| 609 | flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; |
| 610 | current += acpi_create_madt_irqoverride(irqovr, 0, 14, 14, flags); |
| 611 | |
| 612 | return current; |
| 613 | } |