| Angel Pons | 560796c | 2020-04-03 01:22:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 2 | |
| 3 | /* DefinitionBlock Statement */ |
| Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 5 | DefinitionBlock ( |
| Elyes HAOUAS | 2bfaabc | 2020-10-01 17:03:55 +0200 | [diff] [blame] | 6 | "dsdt.aml", |
| Elyes HAOUAS | 37509d7 | 2020-10-01 17:11:56 +0200 | [diff] [blame^] | 7 | "DSDT", |
| Elyes HAOUAS | 90d00de | 2020-10-05 16:38:53 +0200 | [diff] [blame] | 8 | ACPI_DSDT_REV_2, |
| Elyes HAOUAS | 6d19a20 | 2018-11-22 11:15:29 +0100 | [diff] [blame] | 9 | OEM_ID, |
| 10 | ACPI_TABLE_CREATOR, |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 11 | 0x00010001 /* OEM Revision */ |
| 12 | ) |
| 13 | { /* Start of ASL file */ |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 14 | |
| 15 | /* Globals for the platform */ |
| 16 | #include "acpi/mainboard.asl" |
| 17 | |
| 18 | /* Describe the USB Overcurrent pins */ |
| 19 | #include "acpi/usb_oc.asl" |
| 20 | |
| 21 | /* PCI IRQ mapping for the Southbridge */ |
| 22 | #include <southbridge/amd/pi/hudson/acpi/pcie.asl> |
| 23 | |
| Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 24 | /* Describe the processor tree (\_SB) */ |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 25 | #include <cpu/amd/pi/00730F01/acpi/cpu.asl> |
| 26 | |
| 27 | /* Contains the supported sleep states for this chipset */ |
| Kyösti Mälkki | 390ba04 | 2017-08-07 21:42:46 +0300 | [diff] [blame] | 28 | #include <southbridge/amd/common/acpi/sleepstates.asl> |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 29 | |
| 30 | /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ |
| 31 | #include "acpi/sleep.asl" |
| 32 | |
| 33 | /* System Bus */ |
| 34 | Scope(\_SB) { /* Start \_SB scope */ |
| Elyes HAOUAS | d37a5bc | 2018-05-28 13:42:22 +0200 | [diff] [blame] | 35 | /* global utility methods expected within the \_SB scope */ |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 36 | #include <arch/x86/acpi/globutil.asl> |
| 37 | |
| 38 | /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ |
| 39 | #include "acpi/routing.asl" |
| 40 | |
| Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 41 | Device(PCI0) { |
| 42 | /* Describe the AMD Northbridge */ |
| 43 | #include <northbridge/amd/pi/00730F01/acpi/northbridge.asl> |
| 44 | |
| 45 | /* Describe the AMD Fusion Controller Hub Southbridge */ |
| 46 | #include <southbridge/amd/pi/hudson/acpi/fch.asl> |
| 47 | } |
| 48 | |
| 49 | /* Describe PCI INT[A-H] for the Southbridge */ |
| 50 | #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> |
| 51 | |
| 52 | } /* End \_SB scope */ |
| 53 | |
| 54 | /* Describe SMBUS for the Southbridge */ |
| 55 | #include <southbridge/amd/pi/hudson/acpi/smbus.asl> |
| 56 | |
| 57 | /* Define the General Purpose Events for the platform */ |
| 58 | #include "acpi/gpe.asl" |
| 59 | |
| 60 | /* Define the System Indicators for the platform */ |
| 61 | #include "acpi/si.asl" |
| 62 | } |
| 63 | /* End of ASL file */ |