Uwe Hermann | c70e9fc | 2010-02-15 23:10:19 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
Uwe Hermann | c70e9fc | 2010-02-15 23:10:19 +0000 | [diff] [blame] | 4 | ## |
| 5 | ## This program is free software; you can redistribute it and/or modify |
| 6 | ## it under the terms of the GNU General Public License as published by |
| 7 | ## the Free Software Foundation; version 2 of the License. |
| 8 | ## |
| 9 | ## This program is distributed in the hope that it will be useful, |
| 10 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | ## GNU General Public License for more details. |
| 13 | ## |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 14 | |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 15 | config NORTHBRIDGE_INTEL_I945 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 16 | bool |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 17 | |
| 18 | if NORTHBRIDGE_INTEL_I945 |
| 19 | |
| 20 | config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy |
| 21 | def_bool y |
Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 22 | select HAVE_DEBUG_RAM_SETUP |
Paul Menzel | ea8f3b4 | 2014-09-21 12:21:36 +0200 | [diff] [blame] | 23 | select VGA |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 24 | select INTEL_GMA_ACPI |
Nico Huber | 561bebf | 2017-01-19 16:28:18 +0100 | [diff] [blame] | 25 | select INTEL_GMA_SSC_ALTERNATE_REF |
Patrick Rudolph | 46cf5c2 | 2017-04-03 19:09:45 +0200 | [diff] [blame] | 26 | select INTEL_EDID |
Nico Huber | ce642f0 | 2017-05-19 15:08:21 +0200 | [diff] [blame] | 27 | select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT |
Arthur Heymans | f266932 | 2018-04-10 15:15:05 +0200 | [diff] [blame] | 28 | select PARALLEL_MP |
Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 29 | |
Arthur Heymans | 48d5b8d | 2020-04-09 11:44:37 +0200 | [diff] [blame] | 30 | config VBOOT |
| 31 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 32 | select VBOOT_SEPARATE_VERSTAGE |
| 33 | |
Kyösti Mälkki | eb5e28f | 2012-02-24 16:08:18 +0200 | [diff] [blame] | 34 | config NORTHBRIDGE_INTEL_SUBTYPE_I945GC |
| 35 | def_bool n |
| 36 | config NORTHBRIDGE_INTEL_SUBTYPE_I945GM |
| 37 | def_bool n |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 38 | |
Stefan Reinauer | bccbbe6 | 2010-12-19 21:20:14 +0000 | [diff] [blame] | 39 | config VGA_BIOS_ID |
Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 40 | string |
Arthur Heymans | a6b0fc9 | 2016-10-16 17:20:35 +0200 | [diff] [blame] | 41 | default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM |
| 42 | default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 43 | |
Nico Huber | 7971582e | 2017-05-20 01:07:48 +0200 | [diff] [blame] | 44 | config I945_LVDS |
| 45 | def_bool n |
| 46 | select MAINBOARD_HAS_NATIVE_VGA_INIT |
| 47 | select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT |
| 48 | help |
| 49 | Selected by mainboards that use native graphics initialization |
| 50 | for the LVDS port. A linear framebuffer is only supported for |
| 51 | LVDS. |
| 52 | |
Arthur Heymans | c5fba2c | 2017-05-10 11:33:44 +0200 | [diff] [blame] | 53 | config MMCONF_BASE_ADDRESS |
| 54 | hex |
| 55 | default 0xf0000000 |
| 56 | |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 57 | config OVERRIDE_CLOCK_DISABLE |
| 58 | bool |
| 59 | default n |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 60 | help |
| 61 | Usually system firmware turns off system memory clock |
| 62 | signals to unused SO-DIMM slots to reduce EMI and power |
| 63 | consumption. |
| 64 | However, some boards do not like unused clock signals to |
| 65 | be disabled. |
| 66 | |
| 67 | config MAXIMUM_SUPPORTED_FREQUENCY |
| 68 | int |
| 69 | default 0 |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 70 | help |
| 71 | If non-zero, this designates the maximum DDR frequency |
| 72 | the board supports, despite what the chipset should be |
| 73 | capable of. |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 74 | |
Peter Stuge | 751508a | 2012-01-27 22:17:09 +0100 | [diff] [blame] | 75 | config CHECK_SLFRCS_ON_RESUME |
| 76 | def_bool n |
| 77 | help |
| 78 | On some boards it may be neccessary to hard reset early |
| 79 | during resume from S3 if the SLFRCS register indicates that |
| 80 | a memory channel is not guaranteed to be in self-refresh. |
| 81 | On other boards the check always creates a false positive, |
| 82 | effectively making it impossible to resume. |
| 83 | |
Arthur Heymans | dce3927 | 2018-04-10 16:08:27 +0200 | [diff] [blame] | 84 | config SMM_RESERVED_SIZE |
| 85 | hex |
| 86 | default 0x100000 |
| 87 | |
Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame] | 88 | endif |