Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Arthur Heymans | e27c013 | 2019-11-12 23:34:13 +0100 | [diff] [blame] | 5 | #include "i945.h" |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 6 | |
Arthur Heymans | e27c013 | 2019-11-12 23:34:13 +0100 | [diff] [blame] | 7 | void bootblock_early_northbridge_init(void) |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 8 | { |
| 9 | uint32_t reg; |
| 10 | |
| 11 | /* |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 12 | * The "io" variant of the config access is explicitly used to setup the PCIEXBAR |
| 13 | * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit |
| 14 | * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is |
| 15 | * the first thing called in the non-asm boot block code. The final assumption is that |
| 16 | * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses. |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 17 | * |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 18 | * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 19 | */ |
| 20 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame^] | 21 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); |
Kyösti Mälkki | 032c23d | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 22 | } |