nb/i945: Improve code formatting
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index d1cf6db..edc2170 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -10,16 +10,13 @@
uint32_t reg;
/*
- * The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true.
- * That way all subsequent non-explicit config accesses use
- * MCFG. This code also assumes that bootblock_northbridge_init() is
- * the first thing called in the non-asm boot block code. The final
- * assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
+ * The "io" variant of the config access is explicitly used to setup the PCIEXBAR
+ * because CONFIG_MMCONF_SUPPORT is set to true. That way all subsequent non-explicit
+ * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
+ * the first thing called in the non-asm boot block code. The final assumption is that
+ * no assembly code is using the CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
*
- * The PCIEXBAR is assumed to live in the memory mapped IO space under
- * 4GiB.
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);