Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 21 | #include <arch/io.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 26 | #include <arch/acpi.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 27 | #include <cbmem.h> |
| 28 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 29 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Vladimir Serbinenko | 421b340 | 2016-02-10 02:39:51 +0100 | [diff] [blame] | 30 | #include <northbridge/intel/sandybridge/raminit.h> |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 31 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 33 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 34 | #include <arch/cpu.h> |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 35 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 36 | #include <halt.h> |
Martin Roth | 356b519 | 2017-06-24 21:53:37 -0600 | [diff] [blame^] | 37 | #if IS_ENABLED(CONFIG_CHROMEOS) |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 38 | #include <vendorcode/google/chromeos/chromeos.h> |
| 39 | #endif |
| 40 | #include <cbfs.h> |
| 41 | |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 42 | void pch_enable_lpc(void) |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 43 | { |
| 44 | /* EC Decode Range Port60/64 and Port62/66 */ |
| 45 | /* Enable EC and PS/2 Keyboard/Mouse*/ |
| 46 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN); |
| 47 | |
| 48 | /* EC Decode Range Port68/6C */ |
| 49 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001); |
| 50 | |
| 51 | /* EC Decode Range Port 380-387 */ |
| 52 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001); |
| 53 | |
| 54 | } |
| 55 | |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 56 | void rcba_config(void) |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 57 | { |
| 58 | u32 reg32; |
| 59 | |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 60 | /* |
| 61 | * GFX INTA -> PIRQA (MSI) |
| 62 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 63 | * D28IP_P2IP ETH0 INTB -> PIRQF |
| 64 | * D28IP_P3IP SDCARD INTC -> PIRQD |
| 65 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 66 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 67 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 68 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 69 | * D31IP_TTIP THRT INTC -> PIRQA |
| 70 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 71 | * |
| 72 | * Trackpad interrupt is edge triggered and cannot be shared. |
| 73 | * TRACKPAD -> PIRQG |
| 74 | |
| 75 | */ |
| 76 | |
| 77 | /* Device interrupt pin register (board specific) */ |
| 78 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 79 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 80 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 81 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | |
| 82 | (INTC << D28IP_P3IP); |
| 83 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 84 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 85 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 86 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 87 | |
| 88 | /* Device interrupt route registers */ |
| 89 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 90 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 91 | DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); |
| 92 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 93 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 94 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 95 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 96 | |
| 97 | /* Enable IOAPIC (generic) */ |
| 98 | RCBA16(OIC) = 0x0100; |
| 99 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 100 | (void) RCBA16(OIC); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 101 | |
| 102 | /* Disable unused devices (board specific) */ |
| 103 | reg32 = RCBA32(FD); |
| 104 | reg32 |= PCH_DISABLE_ALWAYS; |
| 105 | /* Disable PCI bridge so MRC does not probe this bus */ |
| 106 | reg32 |= PCH_DISABLE_P2P; |
| 107 | RCBA32(FD) = reg32; |
| 108 | } |
| 109 | |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 110 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
Vladimir Serbinenko | 4a84e47 | 2016-02-10 02:51:48 +0100 | [diff] [blame] | 111 | /* enabled power usb oc pin */ |
| 112 | { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ |
| 113 | { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ |
| 114 | { 1, 0, -1 }, /* P2: Camera (no OC) */ |
| 115 | { 0, 0, -1 }, /* P3: Empty */ |
| 116 | { 0, 0, -1 }, /* P4: Empty */ |
| 117 | { 0, 0, -1 }, /* P5: Empty */ |
| 118 | { 0, 0, -1 }, /* P6: Empty */ |
| 119 | { 0, 0, -1 }, /* P7: Empty */ |
| 120 | { 0, 0, -1 }, /* P8: Empty */ |
| 121 | { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ |
| 122 | { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ |
| 123 | { 0, 0, -1 }, /* P11: Empty */ |
| 124 | { 0, 0, -1 }, /* P12: Empty */ |
| 125 | { 0, 0, -1 }, /* P13: Empty */ |
Alexandru Gagniuc | 83b05eb | 2015-02-15 14:09:21 -0600 | [diff] [blame] | 126 | }; |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 127 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 128 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) { |
| 129 | read_spd(&spd[0], 0x50, id_only); |
| 130 | read_spd(&spd[2], 0x52, id_only); |
Stefan Reinauer | d7bd4eb | 2013-02-11 11:11:36 -0800 | [diff] [blame] | 131 | } |
Vladimir Serbinenko | 609bd94 | 2016-01-31 14:00:54 +0100 | [diff] [blame] | 132 | |
| 133 | void mainboard_early_init(int s3resume) { |
| 134 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 135 | |
| 136 | void mainboard_config_superio(void) |
| 137 | { |
| 138 | } |
Vladimir Serbinenko | 421b340 | 2016-02-10 02:39:51 +0100 | [diff] [blame] | 139 | |
| 140 | |
| 141 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 142 | { |
| 143 | struct pei_data pei_data_template = { |
| 144 | .pei_version = PEI_VERSION, |
| 145 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 146 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
| 147 | .epbar = DEFAULT_EPBAR, |
| 148 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 149 | .smbusbar = SMBUS_IO_BASE, |
| 150 | .wdbbar = 0x4000000, |
| 151 | .wdbsize = 0x1000, |
| 152 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 153 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
| 154 | .pmbase = DEFAULT_PMBASE, |
| 155 | .gpiobase = DEFAULT_GPIOBASE, |
| 156 | .thermalbase = 0xfed08000, |
| 157 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 158 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 159 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 160 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 161 | .ec_present = 1, |
| 162 | .ddr3lv_support = 0, |
| 163 | // 0 = leave channel enabled |
| 164 | // 1 = disable dimm 0 on channel |
| 165 | // 2 = disable dimm 1 on channel |
| 166 | // 3 = disable dimm 0+1 on channel |
| 167 | .dimm_channel0_disabled = 2, |
| 168 | .dimm_channel1_disabled = 2, |
| 169 | .max_ddr3_freq = 1600, |
| 170 | .usb_port_config = { |
| 171 | /* enabled usb oc pin length */ |
| 172 | { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ |
| 173 | { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ |
| 174 | { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ |
| 175 | { 0, 0, 0x0000 }, /* P3: Empty */ |
| 176 | { 0, 0, 0x0000 }, /* P4: Empty */ |
| 177 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 178 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 179 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 180 | { 0, 4, 0x0000 }, /* P8: Empty */ |
| 181 | { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ |
| 182 | { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ |
| 183 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 184 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 185 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 186 | }, |
| 187 | .ddr_refresh_rate_config = 2, /* Force double refresh rate */ |
| 188 | }; |
| 189 | *pei_data = pei_data_template; |
| 190 | } |