blob: 7be053748480bb112409958c9cf96f9dd00ef498 [file] [log] [blame]
Myles Watson34261952010-03-19 02:33:40 +00001#include <lib.h> /* Prototypes */
Stefan Reinauer7ce8c542005-12-02 21:52:30 +00002
3#ifndef RAMINIT_SYSINFO
4 #define RAMINIT_SYSINFO 0
5#endif
6
7static inline void print_debug_sdram_8(const char *strval, uint32_t val)
8{
9#if CONFIG_USE_INIT
10 printk_debug("%s%02x\r\n", strval, val);
11#else
12 print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
13#endif
14}
15
Eric Biederman8ca8d762003-04-22 19:02:15 +000016/* Setup SDRAM */
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000017#if RAMINIT_SYSINFO == 1
18void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo)
19#else
Eric Biederman2c018fb2003-07-21 20:13:45 +000020void sdram_initialize(int controllers, const struct mem_controller *ctrl)
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000021#endif
Eric Biederman8ca8d762003-04-22 19:02:15 +000022{
Eric Biederman2c018fb2003-07-21 20:13:45 +000023 int i;
Eric Biederman8ca8d762003-04-22 19:02:15 +000024 /* Set the registers we can set once to reasonable values */
Eric Biederman2c018fb2003-07-21 20:13:45 +000025 for(i = 0; i < controllers; i++) {
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000026 print_debug_sdram_8("Ram1.",i);
27
28 #if RAMINIT_SYSINFO == 1
29 sdram_set_registers(ctrl + i , sysinfo);
30 #else
Eric Biederman2c018fb2003-07-21 20:13:45 +000031 sdram_set_registers(ctrl + i);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000032 #endif
Eric Biederman2c018fb2003-07-21 20:13:45 +000033 }
Eric Biederman8ca8d762003-04-22 19:02:15 +000034
Eric Biederman8ca8d762003-04-22 19:02:15 +000035 /* Now setup those things we can auto detect */
Eric Biederman2c018fb2003-07-21 20:13:45 +000036 for(i = 0; i < controllers; i++) {
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000037 print_debug_sdram_8("Ram2.",i);
38
39 #if RAMINIT_SYSINFO == 1
40 sdram_set_spd_registers(ctrl + i , sysinfo);
41 #else
42 sdram_set_spd_registers(ctrl + i);
43 #endif
44
Eric Biederman2c018fb2003-07-21 20:13:45 +000045 }
Eric Biederman8ca8d762003-04-22 19:02:15 +000046
Eric Biederman8ca8d762003-04-22 19:02:15 +000047 /* Now that everything is setup enable the SDRAM.
Stefan Reinauerbba53ed2008-08-01 11:36:40 +000048 * Some chipsets do the work for us while on others
Eric Biederman8ca8d762003-04-22 19:02:15 +000049 * we need to it by hand.
50 */
Eric Biederman2c018fb2003-07-21 20:13:45 +000051 print_debug("Ram3\r\n");
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000052
53 #if RAMINIT_SYSINFO == 1
54 sdram_enable(controllers, ctrl, sysinfo);
55 #else
Eric Biederman2c018fb2003-07-21 20:13:45 +000056 sdram_enable(controllers, ctrl);
Stefan Reinauer7ce8c542005-12-02 21:52:30 +000057 #endif
Eric Biederman8ca8d762003-04-22 19:02:15 +000058
59 print_debug("Ram4\r\n");
Eric Biederman8ca8d762003-04-22 19:02:15 +000060}