- First pass at s2880 support.
- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/sdram/generic_sdram.c b/src/sdram/generic_sdram.c
index 7bd801a..9ec8122 100644
--- a/src/sdram/generic_sdram.c
+++ b/src/sdram/generic_sdram.c
@@ -7,22 +7,31 @@
}
/* Setup SDRAM */
-void sdram_initialize(const struct mem_controller *ctrl)
+void sdram_initialize(int controllers, const struct mem_controller *ctrl)
{
- print_debug("Ram1\r\n");
+ int i;
/* Set the registers we can set once to reasonable values */
- sdram_set_registers(ctrl);
+ for(i = 0; i < controllers; i++) {
+ print_debug("Ram1.");
+ print_debug_hex8(i);
+ print_debug("\r\n");
+ sdram_set_registers(ctrl + i);
+ }
- print_debug("Ram2\r\n");
/* Now setup those things we can auto detect */
- sdram_set_spd_registers(ctrl);
+ for(i = 0; i < controllers; i++) {
+ print_debug("Ram2.");
+ print_debug_hex8(i);
+ print_debug("\r\n");
+ sdram_set_spd_registers(ctrl + i);
+ }
- print_debug("Ram3\r\n");
/* Now that everything is setup enable the SDRAM.
* Some chipsets do the work for use while on others
* we need to it by hand.
*/
- sdram_enable(ctrl);
+ print_debug("Ram3\r\n");
+ sdram_enable(controllers, ctrl);
print_debug("Ram4\r\n");
}