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Stefan Reinauereca92fb2006-08-23 14:28:37 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Stefan Reinauereca92fb2006-08-23 14:28:37 +00003 *
4 * Copyright (C) 2005 Digital Design Corporation
Uwe Hermann998a57c2006-11-22 11:41:32 +00005 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Stefan Reinauereca92fb2006-08-23 14:28:37 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010019 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauereca92fb2006-08-23 14:28:37 +000020 */
21
Uwe Hermann998a57c2006-11-22 11:41:32 +000022/*
23 * Serial Presence Detect (SPD) data stored on SDRAM modules.
24 *
25 * Datasheet:
26 * - Name: PC SDRAM Serial Presence Detect (SPD) Specification
27 * Revision 1.2A, December, 1997
28 * - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf
29 *
30 * Datasheet (alternative):
31 * - Name: SERIAL PRESENCE DETECT STANDARD, General Standard
32 * JEDEC Standard No. 21-C
33 * - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF
34 */
Stefan Reinauereca92fb2006-08-23 14:28:37 +000035
Uwe Hermann998a57c2006-11-22 11:41:32 +000036#ifndef _SPD_H_
37#define _SPD_H_
Stefan Reinauereca92fb2006-08-23 14:28:37 +000038
Uwe Hermann998a57c2006-11-22 11:41:32 +000039/* Byte numbers. */
40#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */
41#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */
42#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */
43#define SPD_NUM_ROWS 3 /* Number of row address bits */
44#define SPD_NUM_COLUMNS 4 /* Number of column address bits */
45#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */
46#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */
47#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */
48#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */
49#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
50#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
51#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */
52#define SPD_REFRESH 12 /* Refresh rate/type */
53#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */
54#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */
55#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */
56#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */
57#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */
58#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */
59#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */
60#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */
61#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */
62#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */
63#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */
64#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */
65#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */
66#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */
67#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */
68#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */
69#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */
70#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */
71#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */
72#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */
73#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */
74#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */
75#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */
Stefan Reinauer951c62f2008-08-01 11:40:16 +000076#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */
Ed Swierkd39aad92008-08-28 18:23:58 +000077#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */
78#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */
79#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */
80#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
81#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */
82#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */
83#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */
84#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */
85#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */
86#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */
Uwe Hermann998a57c2006-11-22 11:41:32 +000087#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */
88#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */
89#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
90#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */
91#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
92#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */
93#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */
94#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */
95#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */
96#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */
97#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
Stefan Reinauereca92fb2006-08-23 14:28:37 +000098
Marc Jonesbc8176c2007-05-04 18:24:55 +000099/* DRAM specifications use the following naming conventions for SPD locations */
100#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME
101#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE
102#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY
103#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
104#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE
105#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME
106#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
107#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
108
109
Uwe Hermann998a57c2006-11-22 11:41:32 +0000110/* SPD_MEMORY_TYPE values. */
Alexandru Gagniuc32610462013-05-21 14:07:41 -0500111enum spd_memory_type {
112 SPD_MEMORY_TYPE_UNDEFINED = 0x00,
113 SPD_MEMORY_TYPE_FPM_DRAM = 0x01,
114 SPD_MEMORY_TYPE_EDO = 0x02,
115 SPD_MEMORY_TYPE_PIPELINED_NIBBLE = 0x03,
116 SPD_MEMORY_TYPE_SDRAM = 0x04,
117 SPD_MEMORY_TYPE_MULTIPLEXED_ROM = 0x05,
118 SPD_MEMORY_TYPE_SGRAM_DDR = 0x06,
119 SPD_MEMORY_TYPE_SDRAM_DDR = 0x07,
120 SPD_MEMORY_TYPE_SDRAM_DDR2 = 0x08,
121 SPD_MEMORY_TYPE_FBDIMM_DDR2 = 0x09,
122 SPD_MEMORY_TYPE_FB_PROBE_DDR2 = 0x0a,
123 SPD_MEMORY_TYPE_SDRAM_DDR3 = 0x0b,
124};
Stefan Reinauereca92fb2006-08-23 14:28:37 +0000125
Uwe Hermann998a57c2006-11-22 11:41:32 +0000126/* SPD_MODULE_VOLTAGE values. */
127#define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */
128#define SPD_VOLTAGE_LVTTL 1 /* LVTTL */
129#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */
130#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */
131#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */
Stefan Reinauereca92fb2006-08-23 14:28:37 +0000132
Uwe Hermann998a57c2006-11-22 11:41:32 +0000133/* SPD_DIMM_CONFIG_TYPE values. */
134#define ERROR_SCHEME_NONE 0
135#define ERROR_SCHEME_PARITY 1
136#define ERROR_SCHEME_ECC 2
Stefan Reinauereca92fb2006-08-23 14:28:37 +0000137
Uwe Hermann998a57c2006-11-22 11:41:32 +0000138/* SPD_ACCEPTABLE_CAS_LATENCIES values. */
139// TODO: Check values.
140#define SPD_CAS_LATENCY_1_0 0x01
141#define SPD_CAS_LATENCY_1_5 0x02
142#define SPD_CAS_LATENCY_2_0 0x04
143#define SPD_CAS_LATENCY_2_5 0x08
144#define SPD_CAS_LATENCY_3_0 0x10
145#define SPD_CAS_LATENCY_3_5 0x20
146#define SPD_CAS_LATENCY_4_0 0x40
Stefan Reinauereca92fb2006-08-23 14:28:37 +0000147
Stefan Reinauer951c62f2008-08-01 11:40:16 +0000148#define SPD_CAS_LATENCY_DDR2_3 (1 << 3)
149#define SPD_CAS_LATENCY_DDR2_4 (1 << 4)
150#define SPD_CAS_LATENCY_DDR2_5 (1 << 5)
151#define SPD_CAS_LATENCY_DDR2_6 (1 << 6)
152
Uwe Hermann998a57c2006-11-22 11:41:32 +0000153/* SPD_SUPPORTED_BURST_LENGTHS values. */
154#define SPD_BURST_LENGTH_1 1
155#define SPD_BURST_LENGTH_2 2
156#define SPD_BURST_LENGTH_4 4
157#define SPD_BURST_LENGTH_8 8
158#define SPD_BURST_LENGTH_PAGE (1 << 7)
Stefan Reinauereca92fb2006-08-23 14:28:37 +0000159
Uwe Hermann998a57c2006-11-22 11:41:32 +0000160/* SPD_MODULE_ATTRIBUTES values. */
161#define MODULE_BUFFERED 1
162#define MODULE_REGISTERED 2
Stefan Reinauereca92fb2006-08-23 14:28:37 +0000163
Patrick Georgi9bd9a902010-11-20 10:31:00 +0000164/* DIMM SPD addresses */
165#define DIMM0 0x50
166#define DIMM1 0x51
167#define DIMM2 0x52
168#define DIMM3 0x53
169#define DIMM4 0x54
170#define DIMM5 0x55
171#define DIMM6 0x56
172#define DIMM7 0x57
173
Uwe Hermannd773fd32010-11-20 20:23:08 +0000174#define RC00 0
175#define RC01 1
176#define RC02 2
177#define RC03 3
178#define RC04 4
179#define RC05 5
180#define RC06 6
181#define RC07 7
182#define RC08 8
183#define RC09 9
184#define RC10 10
185#define RC11 11
186#define RC12 12
187#define RC13 13
188#define RC14 14
189#define RC15 15
190#define RC16 16
191#define RC17 17
192#define RC18 18
193#define RC19 19
194#define RC20 20
195#define RC21 21
196#define RC22 22
197#define RC23 23
198#define RC24 24
199#define RC25 25
200#define RC26 26
201#define RC27 27
202#define RC28 28
203#define RC29 29
204#define RC30 30
205#define RC31 31
Stefan Reinauereca92fb2006-08-23 14:28:37 +0000206
Uwe Hermannd773fd32010-11-20 20:23:08 +0000207#define RC32 32
208#define RC33 33
209#define RC34 34
210#define RC35 35
211#define RC36 36
212#define RC37 37
213#define RC38 38
214#define RC39 39
215#define RC40 40
216#define RC41 41
217#define RC42 42
218#define RC43 43
219#define RC44 44
220#define RC45 45
221#define RC46 46
222#define RC47 47
223#define RC48 48
224#define RC49 49
225#define RC50 50
226#define RC51 51
227#define RC52 52
228#define RC53 53
229#define RC54 54
230#define RC55 55
231#define RC56 56
232#define RC57 57
233#define RC58 58
234#define RC59 59
235#define RC60 60
236#define RC61 61
237#define RC62 62
238#define RC63 63
239
240#endif