Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | 25509ee | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <arch/acpi.h> |
| 24 | #include <bootstate.h> |
| 25 | #include <cbmem.h> |
| 26 | #include <console/console.h> |
| 27 | #include <cpu/x86/smm.h> |
| 28 | #include <device/device.h> |
| 29 | #include <device/pci.h> |
| 30 | #include <device/pci_ids.h> |
| 31 | #include <pc80/mc146818rtc.h> |
| 32 | #include <drivers/uart/uart8250reg.h> |
| 33 | |
| 34 | #include <soc/iomap.h> |
| 35 | #include <soc/irq.h> |
| 36 | #include <soc/lpc.h> |
| 37 | #include <soc/nvs.h> |
| 38 | #include <soc/pci_devs.h> |
| 39 | #include <soc/pmc.h> |
| 40 | #include <soc/ramstage.h> |
| 41 | #include <soc/spi.h> |
| 42 | #include "chip.h" |
| 43 | |
| 44 | static inline void |
| 45 | add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) |
| 46 | { |
| 47 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 48 | } |
| 49 | |
| 50 | static void sc_add_mmio_resources(device_t dev) |
| 51 | { |
| 52 | add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 53 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 54 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 55 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 56 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 57 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 58 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 59 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
| 60 | } |
| 61 | |
| 62 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 63 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 64 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 65 | |
| 66 | static inline int io_range_in_default(int base, int size) |
| 67 | { |
| 68 | /* Does it start above the range? */ |
| 69 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 70 | return 0; |
| 71 | |
| 72 | /* Is it entirely contained? */ |
| 73 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 74 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 75 | return 1; |
| 76 | |
| 77 | /* This will return not in range for partial overlaps. */ |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | /* |
| 82 | * Note: this function assumes there is no overlap with the default LPC device's |
| 83 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 84 | */ |
| 85 | static void sc_add_io_resource(device_t dev, int base, int size, int index) |
| 86 | { |
| 87 | struct resource *res; |
| 88 | |
| 89 | if (io_range_in_default(base, size)) |
| 90 | return; |
| 91 | |
| 92 | res = new_resource(dev, index); |
| 93 | res->base = base; |
| 94 | res->size = size; |
| 95 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 96 | } |
| 97 | |
| 98 | static void sc_add_io_resources(device_t dev) |
| 99 | { |
| 100 | struct resource *res; |
| 101 | |
| 102 | /* Add the default claimed IO range for the LPC device. */ |
| 103 | res = new_resource(dev, 0); |
| 104 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 105 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 106 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 107 | |
| 108 | /* GPIO */ |
| 109 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); |
| 110 | |
| 111 | /* ACPI */ |
| 112 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); |
| 113 | } |
| 114 | |
| 115 | static void sc_read_resources(device_t dev) |
| 116 | { |
| 117 | /* Get the normal PCI resources of this device. */ |
| 118 | pci_dev_read_resources(dev); |
| 119 | |
| 120 | /* Add non-standard MMIO resources. */ |
| 121 | sc_add_mmio_resources(dev); |
| 122 | |
| 123 | /* Add IO resources. */ |
| 124 | sc_add_io_resources(dev); |
| 125 | } |
| 126 | |
| 127 | static void sc_rtc_init(void) |
| 128 | { |
| 129 | uint32_t gen_pmcon1; |
| 130 | int rtc_fail; |
| 131 | struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 132 | |
| 133 | if (ps != NULL) { |
| 134 | gen_pmcon1 = ps->gen_pmcon1; |
| 135 | } else { |
| 136 | gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); |
| 137 | } |
| 138 | |
| 139 | rtc_fail = !!(gen_pmcon1 & RPS); |
| 140 | |
| 141 | if (rtc_fail) { |
| 142 | printk(BIOS_DEBUG, "RTC failure.\n"); |
| 143 | } |
| 144 | |
| 145 | cmos_init(rtc_fail); |
| 146 | } |
| 147 | |
| 148 | /* |
| 149 | * The UART hardware loses power while in suspend. Because of this the kernel |
| 150 | * can hang because it doesn't re-initialize serial ports it is using for |
| 151 | * consoles at resume time. The following function configures the UART |
| 152 | * if the hardware is enabled though it may not be the correct baud rate |
| 153 | * or configuration. This is definitely a hack, but it helps the kernel |
| 154 | * along. |
| 155 | */ |
| 156 | static void com1_configure_resume(device_t dev) |
| 157 | { |
| 158 | const uint16_t port = 0x3f8; |
| 159 | |
| 160 | /* Is the UART I/O port enabled? */ |
| 161 | if (!(pci_read_config32(dev, UART_CONT) & 1)) |
| 162 | return; |
| 163 | |
| 164 | /* Disable interrupts */ |
| 165 | outb(0x0, port + UART8250_IER); |
| 166 | |
| 167 | /* Enable FIFOs */ |
| 168 | outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR); |
| 169 | |
| 170 | /* assert DTR and RTS so the other end is happy */ |
| 171 | outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR); |
| 172 | |
| 173 | /* DLAB on */ |
| 174 | outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR); |
| 175 | |
| 176 | /* Set Baud Rate Divisor. 1 ==> 115200 Baud */ |
| 177 | outb(1, port + UART8250_DLL); |
| 178 | outb(0, port + UART8250_DLM); |
| 179 | |
| 180 | /* Set to 3 for 8N1 */ |
| 181 | outb(3, port + UART8250_LCR); |
| 182 | } |
| 183 | |
| 184 | static void sc_init(device_t dev) |
| 185 | { |
| 186 | int i; |
| 187 | u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); |
| 188 | u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20; |
| 189 | u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); |
| 190 | u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); |
| 191 | const struct baytrail_irq_route *ir = &global_baytrail_irq_route; |
| 192 | struct soc_intel_baytrail_config *config = dev->chip_info; |
| 193 | |
| 194 | /* Set up the PIRQ PIC routing based on static config. */ |
| 195 | for (i = 0; i < NUM_PIRQS; i++) { |
| 196 | write8(pr_base + i, ir->pic[i]); |
| 197 | } |
| 198 | /* Set up the per device PIRQ routing base on static config. */ |
| 199 | for (i = 0; i < NUM_IR_DEVS; i++) { |
| 200 | write16(ir_base + i, ir->pcidev[i]); |
| 201 | } |
| 202 | |
| 203 | /* Route SCI to IRQ9 */ |
| 204 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
| 205 | |
| 206 | sc_rtc_init(); |
| 207 | |
| 208 | if (config->disable_slp_x_stretch_sus_fail) { |
| 209 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
| 210 | write32(gen_pmcon1, |
| 211 | read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 212 | } else { |
| 213 | write32(gen_pmcon1, |
| 214 | read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
| 215 | } |
| 216 | |
| 217 | if (acpi_is_wakeup_s3()) |
| 218 | com1_configure_resume(dev); |
| 219 | } |
| 220 | |
| 221 | /* |
| 222 | * Common code for the south cluster devices. |
| 223 | */ |
| 224 | |
| 225 | /* Set bit in function disable register to hide this device. */ |
| 226 | static void sc_disable_devfn(device_t dev) |
| 227 | { |
| 228 | u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); |
| 229 | u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
| 230 | uint32_t mask = 0; |
| 231 | uint32_t mask2 = 0; |
| 232 | |
| 233 | switch (dev->path.pci.devfn) { |
| 234 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 235 | mask |= SDIO_DIS; |
| 236 | break; |
| 237 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 238 | mask |= SD_DIS; |
| 239 | break; |
| 240 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 241 | mask |= SATA_DIS; |
| 242 | break; |
| 243 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 244 | mask |= XHCI_DIS; |
| 245 | /* Disable super speed PHY when XHCI is not available. */ |
| 246 | mask2 |= USH_SS_PHY_DIS; |
| 247 | break; |
| 248 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 249 | mask |= LPE_DIS; |
| 250 | break; |
| 251 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 252 | mask |= MMC_DIS; |
| 253 | break; |
| 254 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 255 | mask |= SIO_DMA1_DIS; |
| 256 | break; |
| 257 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 258 | mask |= I2C1_DIS; |
| 259 | break; |
| 260 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 261 | mask |= I2C1_DIS; |
| 262 | break; |
| 263 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 264 | mask |= I2C3_DIS; |
| 265 | break; |
| 266 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 267 | mask |= I2C4_DIS; |
| 268 | break; |
| 269 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 270 | mask |= I2C5_DIS; |
| 271 | break; |
| 272 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 273 | mask |= I2C6_DIS; |
| 274 | break; |
| 275 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 276 | mask |= I2C7_DIS; |
| 277 | break; |
| 278 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
| 279 | mask |= TXE_DIS; |
| 280 | break; |
| 281 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 282 | mask |= HDA_DIS; |
| 283 | break; |
| 284 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 285 | mask |= PCIE_PORT1_DIS; |
| 286 | break; |
| 287 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 288 | mask |= PCIE_PORT2_DIS; |
| 289 | break; |
| 290 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 291 | mask |= PCIE_PORT3_DIS; |
| 292 | break; |
| 293 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 294 | mask |= PCIE_PORT4_DIS; |
| 295 | break; |
| 296 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 297 | mask |= EHCI_DIS; |
| 298 | break; |
| 299 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 300 | mask |= SIO_DMA2_DIS; |
| 301 | break; |
| 302 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 303 | mask |= PWM1_DIS; |
| 304 | break; |
| 305 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 306 | mask |= PWM2_DIS; |
| 307 | break; |
| 308 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 309 | mask |= HSUART1_DIS; |
| 310 | break; |
| 311 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 312 | mask |= HSUART2_DIS; |
| 313 | break; |
| 314 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 315 | mask |= SPI_DIS; |
| 316 | break; |
| 317 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 318 | mask2 |= SMBUS_DIS; |
| 319 | break; |
| 320 | } |
| 321 | |
| 322 | if (mask != 0) { |
| 323 | write32(func_dis, read32(func_dis) | mask); |
| 324 | /* Ensure posted write hits. */ |
| 325 | read32(func_dis); |
| 326 | } |
| 327 | |
| 328 | if (mask2 != 0) { |
| 329 | write32(func_dis2, read32(func_dis2) | mask2); |
| 330 | /* Ensure posted write hits. */ |
| 331 | read32(func_dis2); |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | static inline void set_d3hot_bits(device_t dev, int offset) |
| 336 | { |
| 337 | uint32_t reg8; |
| 338 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 339 | reg8 = pci_read_config8(dev, offset + 4); |
| 340 | reg8 |= 0x3; |
| 341 | pci_write_config8(dev, offset + 4, reg8); |
| 342 | } |
| 343 | |
| 344 | /* Parts of the audio subsystem are powered by the HDA device. Therefore, one |
| 345 | * cannot put HDA into D3Hot. Instead perform this workaround to make some of |
| 346 | * the audio paths work for LPE audio. */ |
| 347 | static void hda_work_around(device_t dev) |
| 348 | { |
| 349 | u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); |
| 350 | |
| 351 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 352 | pci_write_config8(dev, 0x43, 0xd7); |
| 353 | |
| 354 | /* Need to set bit 0 of GCTL to take the device out of reset. However, |
| 355 | * that requires setting up the 64-bit BAR. */ |
| 356 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 357 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
| 358 | pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
| 359 | write32(gctl, read32(gctl) | 0x1); |
| 360 | pci_write_config8(dev, PCI_COMMAND, 0); |
| 361 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 362 | } |
| 363 | |
| 364 | static int place_device_in_d3hot(device_t dev) |
| 365 | { |
| 366 | unsigned offset; |
| 367 | |
| 368 | /* Parts of the HDA block are used for LPE audio as well. |
| 369 | * Therefore assume the HDA will never be put into D3Hot. */ |
| 370 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 371 | hda_work_around(dev); |
| 372 | return 0; |
| 373 | } |
| 374 | |
| 375 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 376 | |
| 377 | if (offset != 0) { |
| 378 | set_d3hot_bits(dev, offset); |
| 379 | return 0; |
| 380 | } |
| 381 | |
| 382 | /* For some reason some of the devices don't have the capability |
| 383 | * pointer set correctly. Work around this by hard coding the offset. */ |
| 384 | switch (dev->path.pci.devfn) { |
| 385 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 386 | offset = 0x80; |
| 387 | break; |
| 388 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 389 | offset = 0x80; |
| 390 | break; |
| 391 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 392 | offset = 0x80; |
| 393 | break; |
| 394 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 395 | offset = 0x80; |
| 396 | break; |
| 397 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 398 | offset = 0x80; |
| 399 | break; |
| 400 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 401 | offset = 0x80; |
| 402 | break; |
| 403 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 404 | offset = 0x80; |
| 405 | break; |
| 406 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 407 | offset = 0x80; |
| 408 | break; |
| 409 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 410 | offset = 0x80; |
| 411 | break; |
| 412 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 413 | offset = 0x80; |
| 414 | break; |
| 415 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 416 | offset = 0x80; |
| 417 | break; |
| 418 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 419 | offset = 0x80; |
| 420 | break; |
| 421 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 422 | offset = 0x80; |
| 423 | break; |
| 424 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 425 | offset = 0x80; |
| 426 | break; |
| 427 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 428 | offset = 0x80; |
| 429 | break; |
| 430 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 431 | offset = 0x80; |
| 432 | break; |
| 433 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 434 | offset = 0x80; |
| 435 | break; |
| 436 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 437 | offset = 0x80; |
| 438 | break; |
| 439 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 440 | offset = 0x70; |
| 441 | break; |
| 442 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 443 | offset = 0x70; |
| 444 | break; |
| 445 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 446 | offset = 0x70; |
| 447 | break; |
| 448 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 449 | offset = 0x50; |
| 450 | break; |
| 451 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 452 | offset = 0x50; |
| 453 | break; |
| 454 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
| 455 | /* TXE cannot be placed in D3Hot. */ |
| 456 | return 0; |
| 457 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 458 | offset = 0xa0; |
| 459 | break; |
| 460 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 461 | offset = 0xa0; |
| 462 | break; |
| 463 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 464 | offset = 0xa0; |
| 465 | break; |
| 466 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 467 | offset = 0xa0; |
| 468 | break; |
| 469 | } |
| 470 | |
| 471 | if (offset != 0) { |
| 472 | set_d3hot_bits(dev, offset); |
| 473 | return 0; |
| 474 | } |
| 475 | |
| 476 | return -1; |
| 477 | } |
| 478 | |
| 479 | /* Common PCI device function disable. */ |
| 480 | void southcluster_enable_dev(device_t dev) |
| 481 | { |
| 482 | uint32_t reg32; |
| 483 | |
| 484 | if (!dev->enabled) { |
| 485 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 486 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 487 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 488 | dev_path(dev), slot, func); |
| 489 | |
| 490 | /* Ensure memory, io, and bus master are all disabled */ |
| 491 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 492 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 493 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 494 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 495 | |
| 496 | /* Place device in D3Hot */ |
| 497 | if (place_device_in_d3hot(dev) < 0) { |
| 498 | printk(BIOS_WARNING, |
| 499 | "Could not place %02x.%01x into D3Hot. " |
| 500 | "Keeping device visible.\n", slot, func); |
| 501 | return; |
| 502 | } |
| 503 | /* Disable this device if possible */ |
| 504 | sc_disable_devfn(dev); |
| 505 | } else { |
| 506 | /* Enable SERR */ |
| 507 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 508 | reg32 |= PCI_COMMAND_SERR; |
| 509 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | static struct device_operations device_ops = { |
| 514 | .read_resources = sc_read_resources, |
| 515 | .set_resources = pci_dev_set_resources, |
| 516 | .enable_resources = NULL, |
| 517 | .init = sc_init, |
| 518 | .enable = southcluster_enable_dev, |
| 519 | .scan_bus = scan_static_bus, |
| 520 | .ops_pci = &soc_pci_ops, |
| 521 | }; |
| 522 | |
| 523 | static const struct pci_driver southcluster __pci_driver = { |
| 524 | .ops = &device_ops, |
| 525 | .vendor = PCI_VENDOR_ID_INTEL, |
| 526 | .device = LPC_DEVID, |
| 527 | }; |
| 528 | |
| 529 | int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) |
| 530 | { |
| 531 | return -1; |
| 532 | } |
| 533 | |
| 534 | static void finalize_chipset(void *unused) |
| 535 | { |
| 536 | u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); |
| 537 | u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS); |
| 538 | u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); |
| 539 | u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); |
| 540 | u8 *spi = (u8 *)SPI_BASE_ADDRESS; |
| 541 | struct spi_config cfg; |
| 542 | |
| 543 | /* Set the lock enable on the BIOS control register. */ |
| 544 | write32(bcr, read32(bcr) | BCR_LE); |
| 545 | |
| 546 | /* Set BIOS lock down bit controlling boot block size and swapping. */ |
| 547 | write32(gcs, read32(gcs) | BILD); |
| 548 | |
| 549 | /* Lock sleep stretching policy and set SMI lock. */ |
| 550 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 551 | |
| 552 | /* Set the CF9 lock. */ |
| 553 | write32(etr, read32(etr) | CF9LOCK); |
| 554 | |
| 555 | if (mainboard_get_spi_config(&cfg) < 0) { |
| 556 | printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); |
| 557 | } else { |
| 558 | write16(spi + PREOP, cfg.preop); |
| 559 | write16(spi + OPTYPE, cfg.optype); |
| 560 | write32(spi + OPMENU0, cfg.opmenu[0]); |
| 561 | write32(spi + OPMENU1, cfg.opmenu[1]); |
| 562 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 563 | write32(spi + UVSCC, cfg.uvscc); |
| 564 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 565 | } |
| 566 | |
| 567 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 568 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 569 | } |
| 570 | |
| 571 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); |
| 572 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); |