Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | 25509ee | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pciexp.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <reg_script.h> |
| 26 | |
| 27 | #include <soc/pci_devs.h> |
| 28 | #include <soc/pcie.h> |
| 29 | #include <soc/ramstage.h> |
| 30 | #include <soc/smm.h> |
| 31 | |
| 32 | #include "chip.h" |
| 33 | |
| 34 | static int pll_en_off; |
| 35 | static uint32_t strpfusecfg; |
| 36 | |
| 37 | static inline int root_port_offset(device_t dev) |
| 38 | { |
| 39 | return PCI_FUNC(dev->path.pci.devfn); |
| 40 | } |
| 41 | |
| 42 | static inline int is_first_port(device_t dev) |
| 43 | { |
| 44 | return root_port_offset(dev) == PCIE_PORT1_FUNC; |
| 45 | } |
| 46 | |
| 47 | static const struct reg_script init_static_before_exit_latency[] = { |
| 48 | /* Disable optimized buffer flush fill and latency tolerant reporting */ |
| 49 | REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), |
| 50 | REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0), |
| 51 | /* Set maximum payload size. */ |
| 52 | REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), |
| 53 | /* Disable transmit datapath flush timer, clear transmit config change |
| 54 | * wait time, clear sideband interface idle counter. */ |
| 55 | REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), |
| 56 | REG_SCRIPT_END, |
| 57 | }; |
| 58 | |
| 59 | static const struct reg_script init_static_after_exit_latency[] = { |
| 60 | /* Set common clock configuration. */ |
| 61 | REG_PCI_OR16(LCTL, CCC), |
| 62 | /* Set NFTS to 0x743a361b */ |
| 63 | REG_PCI_WRITE32(NFTS, 0x743a361b), |
| 64 | /* Set common clock latency to 0x3 */ |
| 65 | REG_PCI_RMW32(MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)), |
| 66 | /* Set relay timer policy. */ |
| 67 | REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), |
| 68 | /* Set IOSF packet fast transmit mode and link speed training policy. */ |
| 69 | REG_PCI_OR16(MPC2, IPF | LSTP), |
| 70 | /* Channel configuration - enable upstream posted split, set non-posted |
| 71 | * and posted request size */ |
| 72 | REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), |
| 73 | /* Completion status replay enable and set TLP grant count */ |
| 74 | REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), |
| 75 | /* Assume no IOAPIC behind root port -- disable EOI forwarding. */ |
| 76 | REG_PCI_OR16(MPC2, EOIFD), |
| 77 | /* Expose AER */ |
| 78 | REG_PCI_RMW32(AERCH, ~0, (1 << 16) | (1 << 0)), |
| 79 | /* set completion timeout to 160ms to 170ms */ |
| 80 | REG_PCI_RMW16(DSTS2, ~CTD, 0x6), |
| 81 | /* Enable AER */ |
| 82 | REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), |
| 83 | /* Read and write back capability registers. */ |
| 84 | REG_PCI_OR32(0x34, 0), |
| 85 | REG_PCI_OR32(0x80, 0), |
| 86 | /* Retrain the link. */ |
| 87 | REG_PCI_OR16(LCTL, RL), |
| 88 | REG_SCRIPT_END, |
| 89 | }; |
| 90 | |
| 91 | static void byt_pcie_init(device_t dev) |
| 92 | { |
| 93 | struct reg_script init_script[] = { |
| 94 | REG_SCRIPT_NEXT(init_static_before_exit_latency), |
| 95 | /* Exit latency configuration based on |
| 96 | * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ |
| 97 | REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, |
| 98 | 2 << (L1EXIT_SHIFT + pll_en_off)), |
| 99 | REG_SCRIPT_NEXT(init_static_after_exit_latency), |
| 100 | /* Disable hot plug, set power to 10W, set slot number. */ |
| 101 | REG_PCI_RMW32(SLCAP, ~(HPC | HPS), |
| 102 | (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | |
| 103 | (root_port_offset(dev) << SLN_SHIFT)), |
| 104 | /* Dynamic clock gating. */ |
| 105 | REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), |
| 106 | REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL), |
| 107 | REG_PCI_OR32(PCIEDBG, SPCE), |
| 108 | REG_SCRIPT_END, |
| 109 | }; |
| 110 | |
| 111 | reg_script_run_on_dev(dev, init_script); |
| 112 | |
| 113 | if (is_first_port(dev)) { |
| 114 | struct soc_intel_baytrail_config *config = dev->chip_info; |
| 115 | uint32_t reg = pci_read_config32(dev, RPPGEN); |
| 116 | reg |= SRDLCGEN | SRDBCGEN; |
| 117 | |
| 118 | if (config && config->clkreq_enable) |
| 119 | reg |= LCLKREQEN | BBCLKREQEN; |
| 120 | |
| 121 | pci_write_config32(dev, RPPGEN, reg); |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | static const struct reg_script no_dev_behind_port[] = { |
| 126 | REG_PCI_OR32(PCIEALC, (1 << 26)), |
| 127 | REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000), |
| 128 | REG_PCI_OR32(PHYCTL4, SQDIS), |
| 129 | REG_SCRIPT_END, |
| 130 | }; |
| 131 | |
| 132 | static void check_port_enabled(device_t dev) |
| 133 | { |
| 134 | int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; |
| 135 | |
| 136 | switch (root_port_offset(dev)) { |
| 137 | case PCIE_PORT1_FUNC: |
| 138 | /* Port 1 cannot be disabled from strapping config. */ |
| 139 | break; |
| 140 | case PCIE_PORT2_FUNC: |
| 141 | /* Port 2 disabled in all configs but 4x1. */ |
| 142 | if (rp_config != 0x0) |
| 143 | dev->enabled = 0; |
| 144 | break; |
| 145 | case PCIE_PORT3_FUNC: |
| 146 | /* Port 3 disabled only in 1x4 config. */ |
| 147 | if (rp_config == 0x3) |
| 148 | dev->enabled = 0; |
| 149 | break; |
| 150 | case PCIE_PORT4_FUNC: |
| 151 | /* Port 4 disabled in 1x4 and 2x2 config. */ |
| 152 | if (rp_config >= 0x2) |
| 153 | dev->enabled = 0; |
| 154 | break; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | static u8 all_ports_no_dev_present(device_t dev) |
| 159 | { |
| 160 | u8 func; |
| 161 | u8 temp = dev->path.pci.devfn; |
| 162 | u8 device_not_present = 1; |
| 163 | u8 data; |
| 164 | |
| 165 | for (func = 1; func < PCIE_ROOT_PORT_COUNT; func++) { |
| 166 | dev->path.pci.devfn &= ~0x7; |
| 167 | dev->path.pci.devfn |= func; |
| 168 | |
| 169 | /* is pcie device there */ |
| 170 | if (pci_read_config32(dev, 0) == 0xFFFFFFFF) |
| 171 | continue; |
| 172 | |
| 173 | data = pci_read_config8(dev, XCAP + 3) | (SI >> 24); |
| 174 | pci_write_config8(dev, XCAP + 3, data); |
| 175 | |
| 176 | /* is any device present */ |
| 177 | if ((pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { |
| 178 | device_not_present = 0; |
| 179 | break; |
| 180 | } |
| 181 | } |
| 182 | |
| 183 | dev->path.pci.devfn = temp; |
| 184 | return device_not_present; |
| 185 | } |
| 186 | |
| 187 | static void check_device_present(device_t dev) |
| 188 | { |
| 189 | /* Set slot implemented. */ |
| 190 | pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); |
| 191 | |
| 192 | /* No device present. */ |
| 193 | if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { |
| 194 | printk(BIOS_DEBUG, "No PCIe device present.\n"); |
| 195 | if (is_first_port(dev)) { |
| 196 | if (all_ports_no_dev_present(dev)) { |
| 197 | reg_script_run_on_dev(dev, no_dev_behind_port); |
| 198 | dev->enabled = 0; |
| 199 | } |
| 200 | } else { |
| 201 | reg_script_run_on_dev(dev, no_dev_behind_port); |
| 202 | dev->enabled = 0; |
| 203 | } |
| 204 | } else if(!dev->enabled) { |
| 205 | /* Port is disabled, but device present. Disable link. */ |
| 206 | pci_write_config32(dev, LCTL, |
| 207 | pci_read_config32(dev, LCTL) | LD); |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | static void byt_pcie_enable(device_t dev) |
| 212 | { |
| 213 | if (is_first_port(dev)) { |
| 214 | struct soc_intel_baytrail_config *config = dev->chip_info; |
| 215 | uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); |
| 216 | pll_en_off = !!(reg & PLL_OFF_EN); |
| 217 | |
| 218 | strpfusecfg = pci_read_config32(dev, STRPFUSECFG); |
| 219 | |
| 220 | if (config && config->pcie_wake_enable) |
| 221 | southcluster_smm_save_param( |
| 222 | SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); |
| 223 | } |
| 224 | |
| 225 | /* Check if device is enabled in strapping. */ |
| 226 | check_port_enabled(dev); |
| 227 | /* Determine if device is behind port. */ |
| 228 | check_device_present(dev); |
| 229 | |
| 230 | southcluster_enable_dev(dev); |
| 231 | } |
| 232 | |
| 233 | static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) |
| 234 | { |
| 235 | static const struct reg_script wait_for_link_active[] = { |
| 236 | REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), |
| 237 | REG_SCRIPT_END, |
| 238 | }; |
| 239 | |
| 240 | /* wait for Link Active with 50ms timeout */ |
| 241 | reg_script_run_on_dev(dev, wait_for_link_active); |
| 242 | |
| 243 | return do_pci_scan_bridge(dev, max, pciexp_scan_bus); |
| 244 | } |
| 245 | |
| 246 | static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) |
| 247 | { |
| 248 | uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); |
| 249 | |
| 250 | if (!didvid) |
| 251 | didvid = pci_read_config32(dev, PCI_VENDOR_ID); |
| 252 | pci_write_config32(dev, 0x94, didvid); |
| 253 | } |
| 254 | |
| 255 | static struct pci_operations pcie_root_ops = { |
| 256 | .set_subsystem = &pcie_root_set_subsystem, |
| 257 | }; |
| 258 | |
| 259 | static struct device_operations device_ops = { |
| 260 | .read_resources = pci_bus_read_resources, |
| 261 | .set_resources = pci_dev_set_resources, |
| 262 | .enable_resources = pci_bus_enable_resources, |
| 263 | .init = byt_pcie_init, |
| 264 | .scan_bus = byt_pciexp_scan_bridge, |
| 265 | .enable = byt_pcie_enable, |
| 266 | .ops_pci = &pcie_root_ops, |
| 267 | }; |
| 268 | |
| 269 | static const unsigned short pci_device_ids[] = { |
| 270 | PCIE_PORT1_DEVID, PCIE_PORT2_DEVID, PCIE_PORT3_DEVID, PCIE_PORT4_DEVID, |
| 271 | 0 |
| 272 | }; |
| 273 | |
| 274 | static const struct pci_driver pcie_root_ports __pci_driver = { |
| 275 | .ops = &device_ops, |
| 276 | .vendor = PCI_VENDOR_ID_INTEL, |
| 277 | .devices = pci_device_ids, |
| 278 | }; |