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Marc Jones738347e2010-09-13 19:24:38 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20//#define SYSTEM_TYPE 0 /* SERVER */
21#define SYSTEM_TYPE 1 /* DESKTOP */
22//#define SYSTEM_TYPE 2 /* MOBILE */
23
Marc Jones738347e2010-09-13 19:24:38 +000024//used by incoherent_ht
25#define FAM10_SCAN_PCI_BUS 0
26#define FAM10_ALLOCATE_IO_RANGE 0
27
Marc Jones738347e2010-09-13 19:24:38 +000028#include <stdint.h>
29#include <string.h>
30#include <device/pci_def.h>
31#include <device/pci_ids.h>
32#include <arch/io.h>
33#include <device/pnp_def.h>
34#include <arch/romcc_io.h>
35#include <cpu/x86/lapic.h>
36#include <console/console.h>
Marc Jones738347e2010-09-13 19:24:38 +000037#include <cpu/amd/model_10xxx_rev.h>
38#include "northbridge/amd/amdfam10/raminit.h"
39#include "northbridge/amd/amdfam10/amdfam10.h"
Patrick Georgid0835952010-10-05 09:07:10 +000040#include <lib.h>
Marc Jones738347e2010-09-13 19:24:38 +000041#include "cpu/x86/lapic/boot_cpu.c"
42#include "northbridge/amd/amdfam10/reset_test.c"
Marc Jones738347e2010-09-13 19:24:38 +000043#include <console/loglevel.h>
44#include "cpu/x86/bist.h"
stepan8301d832010-12-08 07:07:33 +000045#include "superio/fintek/f71859/early_serial.c"
Patrick Georgi5692c572010-10-05 13:40:31 +000046#include <usbdebug.h>
Marc Jones738347e2010-09-13 19:24:38 +000047#include "cpu/x86/mtrr/earlymtrr.c"
48#include <cpu/amd/mtrr.h>
49#include "northbridge/amd/amdfam10/setup_resource_map.c"
stepan836ae292010-12-08 05:42:47 +000050#include "southbridge/amd/rs780/early_setup.c"
51#include "southbridge/amd/sb700/early_setup.c"
Marc Jones738347e2010-09-13 19:24:38 +000052#include "northbridge/amd/amdfam10/debug.c"
53
Uwe Hermann7b997052010-11-21 22:47:22 +000054#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
55
56static void activate_spd_rom(const struct mem_controller *ctrl) { }
Marc Jones738347e2010-09-13 19:24:38 +000057
58static int spd_read_byte(u32 device, u32 address)
59{
Uwe Hermann7b997052010-11-21 22:47:22 +000060 return smbus_read_byte(device, address);
Marc Jones738347e2010-09-13 19:24:38 +000061}
62
63#include "northbridge/amd/amdfam10/amdfam10.h"
Marc Jones738347e2010-09-13 19:24:38 +000064#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
stepan8301d832010-12-08 07:07:33 +000065#include "northbridge/amd/amdfam10/pci.c"
Marc Jones738347e2010-09-13 19:24:38 +000066#include "resourcemap.c"
67#include "cpu/amd/quadcore/quadcore.c"
Marc Jones738347e2010-09-13 19:24:38 +000068#include "cpu/amd/car/post_cache_as_ram.c"
69#include "cpu/amd/microcode/microcode.c"
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +000070
71#if CONFIG_UPDATE_CPU_MICROCODE
Marc Jones738347e2010-09-13 19:24:38 +000072#include "cpu/amd/model_10xxx/update_microcode.c"
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +000073#endif
74
Marc Jones738347e2010-09-13 19:24:38 +000075#include "cpu/amd/model_10xxx/init_cpus.c"
Marc Jones738347e2010-09-13 19:24:38 +000076#include "northbridge/amd/amdfam10/early_ht.c"
Patrick Georgi9bd9a902010-11-20 10:31:00 +000077#include <spd.h>
Marc Jones738347e2010-09-13 19:24:38 +000078
Marc Jones738347e2010-09-13 19:24:38 +000079void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
80{
Marc Jones738347e2010-09-13 19:24:38 +000081 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
82 static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
Uwe Hermann7b997052010-11-21 22:47:22 +000083 u32 bsp_apicid = 0, val;
Marc Jones738347e2010-09-13 19:24:38 +000084 msr_t msr;
85
86 if (!cpu_init_detectedx && boot_cpu()) {
87 /* Nothing special needs to be done to find bus 0 */
88 /* Allow the HT devices to be found */
89 /* mov bsp to bus 0xff when > 8 nodes */
90 set_bsp_node_CHtExtNodeCfgEn();
91 enumerate_ht_chain();
Marc Jones738347e2010-09-13 19:24:38 +000092 sb700_pci_port80();
93 }
94
95 post_code(0x30);
96
97 if (bist == 0) {
98 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
99 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
100 }
101
102 post_code(0x32);
103
104 enable_rs780_dev8();
105 sb700_lpc_init();
106
107 f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
108 uart_init();
Uwe Hermannb015d022010-09-24 18:18:20 +0000109
110#if CONFIG_USBDEBUG
Uwe Hermannae3f2b32010-10-02 20:36:26 +0000111 sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
Uwe Hermannb015d022010-09-24 18:18:20 +0000112 early_usbdebug_init();
113#endif
114
Marc Jones738347e2010-09-13 19:24:38 +0000115 console_init();
116 printk(BIOS_DEBUG, "\n");
117
118// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
119
120 /* Halt if there was a built in self test failure */
121 report_bist_failure(bist);
122
123 // Load MPB
124 val = cpuid_eax(1);
125 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
126 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
127 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
128 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
129
130 /* Setup sysinfo defaults */
131 set_sysinfo_in_ram(0);
132
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +0000133#if CONFIG_UPDATE_CPU_MICROCODE
Marc Jones738347e2010-09-13 19:24:38 +0000134 update_microcode(val);
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +0000135#endif
Marc Jones738347e2010-09-13 19:24:38 +0000136 post_code(0x33);
137
138 cpuSetAMDMSR();
139 post_code(0x34);
140
141 amd_ht_init(sysinfo);
142 post_code(0x35);
143
144 /* Setup nodes PCI space and start core 0 AP init. */
145 finalize_node_setup(sysinfo);
146
147 /* Setup any mainboard PCI settings etc. */
148 setup_mb_resource_map();
149 post_code(0x36);
150
151 /* wait for all the APs core0 started by finalize_node_setup. */
152 /* FIXME: A bunch of cores are going to start output to serial at once.
153 It would be nice to fixup prink spinlocks for ROM XIP mode.
154 I think it could be done by putting the spinlock flag in the cache
155 of the BSP located right after sysinfo.
156 */
157 wait_all_core0_started();
158
159 #if CONFIG_LOGICAL_CPUS==1
160 /* Core0 on each node is configured. Now setup any additional cores. */
161 printk(BIOS_DEBUG, "start_other_cores()\n");
162 start_other_cores();
163 post_code(0x37);
164 wait_all_other_cores_started(bsp_apicid);
165 #endif
166
167 post_code(0x38);
168
169 /* run _early_setup before soft-reset. */
170 rs780_early_setup();
171 sb700_early_setup();
172
Patrick Georgi76e81522010-11-16 21:25:29 +0000173 #if CONFIG_SET_FIDVID
Marc Jones738347e2010-09-13 19:24:38 +0000174 msr = rdmsr(0xc0010071);
175 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
176
177 /* FIXME: The sb fid change may survive the warm reset and only
178 need to be done once.*/
179 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
180
181 post_code(0x39);
182
183 if (!warm_reset_detect(0)) { // BSP is node 0
184 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
185 } else {
186 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
187 }
188
189 post_code(0x3A);
190
191 /* show final fid and vid */
192 msr=rdmsr(0xc0010071);
193 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
194 #endif
195
196 rs780_htinit();
197
198 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
199 if (!warm_reset_detect(0)) {
200 print_info("...WARM RESET...\n\n\n");
201 soft_reset();
202 die("After soft_reset_x - shouldn't see this message!!!\n");
203 }
204
205 post_code(0x3B);
206
207 /* It's the time to set ctrl in sysinfo now; */
208 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
209 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
210
211 post_code(0x40);
212
213// die("Die Before MCT init.");
214
215 printk(BIOS_DEBUG, "raminit_amdmct()\n");
216 raminit_amdmct(sysinfo);
217 post_code(0x41);
218
219/*
220 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
221 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
222 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
223 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
224*/
225
Marc Jones738347e2010-09-13 19:24:38 +0000226// die("After MCT init before CAR disabled.");
227
228 rs780_before_pci_init();
229 sb700_before_pci_init();
230
231 post_code(0x42);
232 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
233 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
234 post_code(0x43); // Should never see this post code.
235}
Scott Duplichan314dd0b2011-03-08 23:01:46 +0000236
237/**
238 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
239 * Description:
240 * This routine is called every time a non-coherent chain is processed.
241 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
242 * swap list. The first part of the list controls the BUID assignment and the
243 * second part of the list provides the device to device linking. Device orientation
244 * can be detected automatically, or explicitly. See documentation for more details.
245 *
246 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
247 * based on each device's unit count.
248 *
249 * Parameters:
250 * @param[in] u8 node = The node on which this chain is located
251 * @param[in] u8 link = The link on the host for this chain
252 * @param[out] u8** list = supply a pointer to a list
253 * @param[out] BOOL result = true to use a manual list
254 * false to initialize the link automatically
255 */
256BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
257{
258 static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
259 /* If the BUID was adjusted in early_ht we need to do the manual override */
260 if ((node == 0) && (link == 0)) { /* BSP SB link */
261 *List = swaplist;
262 return 1;
263 }
264
265 return 0;
266}