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Angel Pons8a3453f2020-04-02 23:48:19 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +02002
3#include <stdint.h>
Arthur Heymans750d57f2020-08-07 22:12:09 +02004#include <cbmem.h>
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +02005#include <cpu/x86/msr.h>
6#include <cpu/x86/mtrr.h>
7#include <cpu/amd/mtrr.h>
8#include <cpu/x86/cache.h>
9#include <string.h>
Kyösti Mälkkid4955f02017-09-08 07:14:17 +030010#include <northbridge/amd/agesa/agesa_helper.h>
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020011
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020012/* TODO: Do we want MTRR_DEF_TYPE_MSR too? */
13static const uint32_t msr_backup[] = {
14 MTRR_FIX_64K_00000,
15 MTRR_FIX_16K_80000,
16 MTRR_FIX_16K_A0000,
17 MTRR_FIX_4K_C0000,
18 MTRR_FIX_4K_C8000,
19 MTRR_FIX_4K_D0000,
20 MTRR_FIX_4K_D8000,
21 MTRR_FIX_4K_E0000,
22 MTRR_FIX_4K_E8000,
23 MTRR_FIX_4K_F0000,
24 MTRR_FIX_4K_F8000,
25 MTRR_PHYS_BASE(0),
26 MTRR_PHYS_MASK(0),
27 MTRR_PHYS_BASE(1),
28 MTRR_PHYS_MASK(1),
29 MTRR_PHYS_BASE(2),
30 MTRR_PHYS_MASK(2),
31 MTRR_PHYS_BASE(3),
32 MTRR_PHYS_MASK(3),
33 MTRR_PHYS_BASE(4),
34 MTRR_PHYS_MASK(4),
35 MTRR_PHYS_BASE(5),
36 MTRR_PHYS_MASK(5),
37 MTRR_PHYS_BASE(6),
38 MTRR_PHYS_MASK(6),
39 MTRR_PHYS_BASE(7),
40 MTRR_PHYS_MASK(7),
41 SYSCFG_MSR,
42 TOP_MEM,
43 TOP_MEM2,
44};
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020045
Arthur Heymans750d57f2020-08-07 22:12:09 +020046void backup_mtrr(void)
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020047{
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020048 msr_t syscfg_msr;
Arthur Heymans750d57f2020-08-07 22:12:09 +020049 msr_t *mtrr_save = (msr_t *)cbmem_add(CBMEM_ID_AGESA_MTRR,
50 sizeof(msr_t) * ARRAY_SIZE(msr_backup));
51 if (!mtrr_save)
52 return;
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020053
54 /* Enable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020055 syscfg_msr = rdmsr(SYSCFG_MSR);
56 syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
57 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020058
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020059 for (int i = 0; i < ARRAY_SIZE(msr_backup); i++)
60 *mtrr_save++ = rdmsr(msr_backup[i]);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020061
62 /* Disable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020063 syscfg_msr = rdmsr(SYSCFG_MSR);
64 syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
65 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020066}
67
68void restore_mtrr(void)
69{
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020070 msr_t syscfg_msr;
Arthur Heymans750d57f2020-08-07 22:12:09 +020071 msr_t *mtrr_save = (msr_t *)cbmem_find(CBMEM_ID_AGESA_MTRR);
72
73 if (!mtrr_save)
74 return;
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020075
76 /* Enable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020077 syscfg_msr = rdmsr(SYSCFG_MSR);
78 syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
79 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020080
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020081 for (int i = 0; i < ARRAY_SIZE(msr_backup); i++)
82 wrmsr(msr_backup[i], *mtrr_save++);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020083
84 /* Disable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020085 syscfg_msr = rdmsr(SYSCFG_MSR);
86 syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
87 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020088}