Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Arthur Heymans | 750d57f | 2020-08-07 22:12:09 +0200 | [diff] [blame] | 4 | #include <cbmem.h> |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 5 | #include <cpu/x86/msr.h> |
| 6 | #include <cpu/x86/mtrr.h> |
| 7 | #include <cpu/amd/mtrr.h> |
| 8 | #include <cpu/x86/cache.h> |
| 9 | #include <string.h> |
Kyösti Mälkki | d4955f0 | 2017-09-08 07:14:17 +0300 | [diff] [blame] | 10 | #include <northbridge/amd/agesa/agesa_helper.h> |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 11 | |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 12 | /* TODO: Do we want MTRR_DEF_TYPE_MSR too? */ |
| 13 | static const uint32_t msr_backup[] = { |
| 14 | MTRR_FIX_64K_00000, |
| 15 | MTRR_FIX_16K_80000, |
| 16 | MTRR_FIX_16K_A0000, |
| 17 | MTRR_FIX_4K_C0000, |
| 18 | MTRR_FIX_4K_C8000, |
| 19 | MTRR_FIX_4K_D0000, |
| 20 | MTRR_FIX_4K_D8000, |
| 21 | MTRR_FIX_4K_E0000, |
| 22 | MTRR_FIX_4K_E8000, |
| 23 | MTRR_FIX_4K_F0000, |
| 24 | MTRR_FIX_4K_F8000, |
| 25 | MTRR_PHYS_BASE(0), |
| 26 | MTRR_PHYS_MASK(0), |
| 27 | MTRR_PHYS_BASE(1), |
| 28 | MTRR_PHYS_MASK(1), |
| 29 | MTRR_PHYS_BASE(2), |
| 30 | MTRR_PHYS_MASK(2), |
| 31 | MTRR_PHYS_BASE(3), |
| 32 | MTRR_PHYS_MASK(3), |
| 33 | MTRR_PHYS_BASE(4), |
| 34 | MTRR_PHYS_MASK(4), |
| 35 | MTRR_PHYS_BASE(5), |
| 36 | MTRR_PHYS_MASK(5), |
| 37 | MTRR_PHYS_BASE(6), |
| 38 | MTRR_PHYS_MASK(6), |
| 39 | MTRR_PHYS_BASE(7), |
| 40 | MTRR_PHYS_MASK(7), |
| 41 | SYSCFG_MSR, |
| 42 | TOP_MEM, |
| 43 | TOP_MEM2, |
| 44 | }; |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 45 | |
Arthur Heymans | 750d57f | 2020-08-07 22:12:09 +0200 | [diff] [blame] | 46 | void backup_mtrr(void) |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 47 | { |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 48 | msr_t syscfg_msr; |
Arthur Heymans | 750d57f | 2020-08-07 22:12:09 +0200 | [diff] [blame] | 49 | msr_t *mtrr_save = (msr_t *)cbmem_add(CBMEM_ID_AGESA_MTRR, |
| 50 | sizeof(msr_t) * ARRAY_SIZE(msr_backup)); |
| 51 | if (!mtrr_save) |
| 52 | return; |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 53 | |
| 54 | /* Enable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 55 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 56 | syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 57 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 58 | |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 59 | for (int i = 0; i < ARRAY_SIZE(msr_backup); i++) |
| 60 | *mtrr_save++ = rdmsr(msr_backup[i]); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 61 | |
| 62 | /* Disable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 63 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 64 | syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 65 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | void restore_mtrr(void) |
| 69 | { |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 70 | msr_t syscfg_msr; |
Arthur Heymans | 750d57f | 2020-08-07 22:12:09 +0200 | [diff] [blame] | 71 | msr_t *mtrr_save = (msr_t *)cbmem_find(CBMEM_ID_AGESA_MTRR); |
| 72 | |
| 73 | if (!mtrr_save) |
| 74 | return; |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 75 | |
| 76 | /* Enable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 77 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 78 | syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 79 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 80 | |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 81 | for (int i = 0; i < ARRAY_SIZE(msr_backup); i++) |
| 82 | wrmsr(msr_backup[i], *mtrr_save++); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 83 | |
| 84 | /* Disable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame] | 85 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 86 | syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 87 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 88 | } |