blob: b91d73d2164091c6865a255c1beb1ce346d3d175 [file] [log] [blame]
Angel Ponsf94ac9a2020-04-05 15:46:48 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Duncan Lauriec88c54c2014-04-30 16:36:13 -07002
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ids.h>
7#include <device/pci_ops.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02008#include <device/mmio.h>
Duncan Lauriec88c54c2014-04-30 16:36:13 -07009#include <soc/intel/common/hda_verb.h>
Julius Werner4ee4bd52014-10-20 13:46:39 -070010#include <soc/ramstage.h>
Matt DeVillierf8960a62016-11-16 23:37:43 -060011#include <soc/igd.h>
Duncan Lauriec88c54c2014-04-30 16:36:13 -070012
13static const u32 minihd_verb_table[] = {
14 /* coreboot specific header */
Matt DeVilliereafa2032019-12-19 19:39:25 -060015 0x80862808, // Codec Vendor / Device ID: Intel Broadwell Mini-HD
16 0x80860101, // Subsystem ID
Duncan Lauriec88c54c2014-04-30 16:36:13 -070017 0x00000004, // Number of jacks
18
19 /* Enable 3rd Pin and Converter Widget */
20 0x00878101,
21
22 /* Pin Widget 5 - PORT B */
23 0x00571C10,
24 0x00571D00,
25 0x00571E56,
26 0x00571F18,
27
28 /* Pin Widget 6 - PORT C */
29 0x00671C20,
30 0x00671D00,
31 0x00671E56,
32 0x00671F18,
33
34 /* Pin Widget 7 - PORT D */
35 0x00771C30,
36 0x00771D00,
37 0x00771E56,
38 0x00771F18,
39
40 /* Disable 3rd Pin and Converter Widget */
41 0x00878100,
42
43 /* Dummy entries to fill out the table */
44 0x00878100,
45 0x00878100,
46};
47
48static void minihd_init(struct device *dev)
49{
50 struct resource *res;
Jacob Garberea61c0e2019-07-22 12:53:27 -060051 u8 *base;
52 u32 reg32;
Duncan Lauriec88c54c2014-04-30 16:36:13 -070053 int codec_mask, i;
54
55 /* Find base address */
56 res = find_resource(dev, PCI_BASE_ADDRESS_0);
57 if (!res)
58 return;
59
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080060 base = res2mmio(res, 0, 0);
61 printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
Duncan Lauriec88c54c2014-04-30 16:36:13 -070062
63 /* Set Bus Master */
Elyes HAOUASb887adf2020-04-29 10:42:34 +020064 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
Duncan Lauriec88c54c2014-04-30 16:36:13 -070065
66 /* Mini-HD configuration */
67 reg32 = read32(base + 0x100c);
68 reg32 &= 0xfffc0000;
69 reg32 |= 0x4;
70 write32(base + 0x100c, reg32);
71
72 reg32 = read32(base + 0x1010);
73 reg32 &= 0xfffc0000;
74 reg32 |= 0x4b;
75 write32(base + 0x1010, reg32);
76
77 /* Init the codec and write the verb table */
78 codec_mask = hda_codec_detect(base);
79
80 if (codec_mask) {
81 for (i = 3; i >= 0; i--) {
82 if (codec_mask & (1 << i))
83 hda_codec_init(base, i,
84 sizeof(minihd_verb_table),
85 minihd_verb_table);
86 }
87 }
Matt DeVillierf8960a62016-11-16 23:37:43 -060088
89 /* Set EM4/EM5 registers */
90 write32(base + 0x0100c, igd_get_reg_em4());
91 write32(base + 0x01010, igd_get_reg_em5());
Duncan Lauriec88c54c2014-04-30 16:36:13 -070092}
93
94static struct device_operations minihd_ops = {
95 .read_resources = &pci_dev_read_resources,
96 .set_resources = &pci_dev_set_resources,
97 .enable_resources = &pci_dev_enable_resources,
98 .init = &minihd_init,
99 .ops_pci = &broadwell_pci_ops,
100};
101
102static const unsigned short pci_device_ids[] = {
103 0x0a0c, /* Haswell */
104 0x160c, /* Broadwell */
105 0
106};
107
108static const struct pci_driver minihd_driver __pci_driver = {
109 .ops = &minihd_ops,
110 .vendor = PCI_VENDOR_ID_INTEL,
111 .devices = pci_device_ids,
112};