Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 - 2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 - 2017 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 18 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | |
| 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/ramstage.h> |
| 27 | #include <soc/sata.h> |
| 28 | |
| 29 | #include "chip.h" |
| 30 | |
| 31 | static void sata_init(struct device *dev) |
| 32 | { |
| 33 | u32 reg32; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 34 | u32 abar; |
| 35 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 36 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 37 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 38 | /* SATA configuration is handled by the FSP */ |
| 39 | |
| 40 | /* Enable BARs */ |
| 41 | pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | |
| 42 | PCI_COMMAND_MEMORY | |
| 43 | PCI_COMMAND_IO); |
| 44 | |
| 45 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
| 46 | |
| 47 | /* Set the controller mode */ |
Stephen Douthit | 2c18ba5 | 2019-08-02 17:05:03 -0400 | [diff] [blame^] | 48 | reg32 = pci_read_config32(dev, SATAGC); |
| 49 | reg32 &= ~SATAGC_AHCI; |
| 50 | pci_write_config32(dev, SATAGC, reg32); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 51 | |
| 52 | /* Initialize AHCI memory-mapped space */ |
| 53 | abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 54 | printk(BIOS_DEBUG, "ABAR: %08X\n", abar); |
| 55 | |
| 56 | /* Enable AHCI Mode */ |
| 57 | reg32 = read32((void *)(abar + 0x04)); |
| 58 | reg32 |= (1 << 31); |
| 59 | write32((void *)(abar + 0x04), reg32); |
| 60 | } |
| 61 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 62 | static void sata_enable(struct device *dev) { /* TODO */ } |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 63 | |
| 64 | static struct device_operations sata_ops = { |
| 65 | .read_resources = pci_dev_read_resources, |
| 66 | .set_resources = pci_dev_set_resources, |
| 67 | .enable_resources = pci_dev_enable_resources, |
| 68 | .init = sata_init, |
| 69 | .enable = sata_enable, |
| 70 | .scan_bus = 0, |
| 71 | .ops_pci = &soc_pci_ops, |
| 72 | }; |
| 73 | |
| 74 | static const unsigned short pci_device_ids[] = { |
Felix Singer | dbc90df | 2019-11-22 00:10:20 +0100 | [diff] [blame] | 75 | PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1, |
| 76 | PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 77 | 0 |
| 78 | }; |
| 79 | |
| 80 | static const struct pci_driver soc_sata __pci_driver = { |
| 81 | .ops = &sata_ops, |
| 82 | .vendor = PCI_VENDOR_ID_INTEL, |
| 83 | .devices = pci_device_ids, |
| 84 | }; |