| Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 - 2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 - 2017 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | |
| 24 | #include <soc/pci_devs.h> |
| 25 | #include <soc/ramstage.h> |
| 26 | #include <soc/sata.h> |
| 27 | |
| 28 | #include "chip.h" |
| 29 | |
| 30 | static void sata_init(struct device *dev) |
| 31 | { |
| 32 | u32 reg32; |
| 33 | u16 reg16; |
| 34 | u32 abar; |
| 35 | |
| 36 | /* Get the chip configuration */ |
| 37 | config_t *config = dev->chip_info; |
| 38 | |
| 39 | printk(BIOS_DEBUG, "SATA: Initializing...\n"); |
| 40 | |
| 41 | if (config == NULL) { |
| 42 | printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); |
| 43 | return; |
| 44 | } |
| 45 | |
| 46 | /* SATA configuration is handled by the FSP */ |
| 47 | |
| 48 | /* Enable BARs */ |
| 49 | pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | |
| 50 | PCI_COMMAND_MEMORY | |
| 51 | PCI_COMMAND_IO); |
| 52 | |
| 53 | printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); |
| 54 | |
| 55 | /* Set the controller mode */ |
| 56 | reg16 = pci_read_config16(dev, SATA_MAP); |
| 57 | reg16 &= ~(3 << 6); |
| 58 | reg16 |= SATA_MAP_AHCI; |
| 59 | pci_write_config16(dev, SATA_MAP, reg16); |
| 60 | |
| 61 | /* Initialize AHCI memory-mapped space */ |
| 62 | abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 63 | printk(BIOS_DEBUG, "ABAR: %08X\n", abar); |
| 64 | |
| 65 | /* Enable AHCI Mode */ |
| 66 | reg32 = read32((void *)(abar + 0x04)); |
| 67 | reg32 |= (1 << 31); |
| 68 | write32((void *)(abar + 0x04), reg32); |
| 69 | } |
| 70 | |
| 71 | static void sata_enable(device_t dev) { /* TODO */ } |
| 72 | |
| 73 | static struct device_operations sata_ops = { |
| 74 | .read_resources = pci_dev_read_resources, |
| 75 | .set_resources = pci_dev_set_resources, |
| 76 | .enable_resources = pci_dev_enable_resources, |
| 77 | .init = sata_init, |
| 78 | .enable = sata_enable, |
| 79 | .scan_bus = 0, |
| 80 | .ops_pci = &soc_pci_ops, |
| 81 | }; |
| 82 | |
| 83 | static const unsigned short pci_device_ids[] = { |
| 84 | AHCI_DEVID, /* DVN SATA AHCI */ |
| 85 | AHCI2_DEVID, /* DVN SATA2 AHCI */ |
| 86 | 0 |
| 87 | }; |
| 88 | |
| 89 | static const struct pci_driver soc_sata __pci_driver = { |
| 90 | .ops = &sata_ops, |
| 91 | .vendor = PCI_VENDOR_ID_INTEL, |
| 92 | .devices = pci_device_ids, |
| 93 | }; |