arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 1 | #define ASSEMBLY 1 |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 2 | #define __PRE_RAM__ |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 3 | |
| 4 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 5 | #include <string.h> |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 6 | #include <device/pci_def.h> |
| 7 | #include <arch/io.h> |
| 8 | #include <device/pnp_def.h> |
| 9 | #include <arch/romcc_io.h> |
| 10 | #include <cpu/x86/lapic.h> |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 11 | #include <stdlib.h> |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 12 | #include "option_table.h" |
| 13 | #include "pc80/mc146818rtc_early.c" |
| 14 | #include "pc80/serial.c" |
| 15 | #include "arch/i386/lib/console.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 16 | #include "lib/ramtest.c" |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 17 | |
Stefan Reinauer | 373511b | 2005-12-02 23:16:01 +0000 | [diff] [blame] | 18 | #include <cpu/amd/model_fxx_rev.h> |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 19 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 20 | #include "southbridge/amd/amd8111/amd8111_early_smbus.c" |
| 21 | #include "northbridge/amd/amdk8/raminit.h" |
| 22 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 23 | #include "lib/delay.c" |
| 24 | |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 25 | #include "cpu/x86/lapic/boot_cpu.c" |
| 26 | #include "northbridge/amd/amdk8/reset_test.c" |
| 27 | #include "northbridge/amd/amdk8/debug.c" |
| 28 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| 29 | |
| 30 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 31 | #include "cpu/x86/bist.h" |
| 32 | |
| 33 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 34 | |
| 35 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 36 | |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 37 | #include "southbridge/amd/amd8111/amd8111_early_ctrl.c" |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 38 | |
| 39 | static void memreset_setup(void) |
| 40 | { |
| 41 | if (is_cpu_pre_c0()) { |
| 42 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 |
| 43 | } |
| 44 | else { |
| 45 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 |
| 46 | } |
| 47 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); |
| 48 | } |
| 49 | |
| 50 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 51 | { |
| 52 | if (is_cpu_pre_c0()) { |
| 53 | udelay(800); |
| 54 | outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 |
| 55 | udelay(90); |
| 56 | } |
| 57 | } |
| 58 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 59 | { |
| 60 | #define SMBUS_HUB 0x18 |
| 61 | int ret; |
| 62 | unsigned device=(ctrl->channel0[0])>>8; |
| 63 | smbus_write_byte(SMBUS_HUB, 0x01, device); |
| 64 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 65 | } |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 66 | #if 0 |
| 67 | static inline void change_i2c_mux(unsigned device) |
| 68 | { |
| 69 | #define SMBUS_HUB 0x18 |
| 70 | int ret; |
| 71 | print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); |
| 72 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
| 73 | print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); |
| 74 | ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 75 | print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); |
| 76 | } |
| 77 | #endif |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 78 | |
| 79 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 80 | { |
| 81 | return smbus_read_byte(device, address); |
| 82 | } |
| 83 | |
Yinghai Lu | 7110f92 | 2006-10-05 06:59:56 +0000 | [diff] [blame] | 84 | #define QRANK_DIMM_SUPPORT 1 |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 85 | |
| 86 | #include "northbridge/amd/amdk8/raminit.c" |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 87 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 88 | #include "lib/generic_sdram.c" |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 89 | |
| 90 | /* tyan does not want the default */ |
| 91 | #include "resourcemap.c" |
| 92 | |
| 93 | #if CONFIG_LOGICAL_CPUS==1 |
| 94 | #define SET_NB_CFG_54 1 |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 95 | #endif |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 96 | #include "cpu/amd/dualcore/dualcore.c" |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 97 | |
| 98 | #define RC0 ((1<<2)<<8) |
| 99 | #define RC1 ((1<<1)<<8) |
| 100 | #define RC2 ((1<<4)<<8) |
| 101 | #define RC3 ((1<<3)<<8) |
| 102 | |
| 103 | #define DIMM0 0x50 |
| 104 | #define DIMM1 0x51 |
| 105 | #define DIMM2 0x52 |
| 106 | #define DIMM3 0x53 |
| 107 | |
| 108 | #include "cpu/amd/car/copy_and_run.c" |
| 109 | |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 110 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 111 | |
| 112 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 113 | |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 114 | #include "southbridge/amd/amd8111/amd8111_enable_rom.c" |
| 115 | #include "northbridge/amd/amdk8/early_ht.c" |
| 116 | |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 117 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 118 | { |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 119 | static const struct mem_controller cpu[] = { |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 120 | { |
| 121 | .node_id = 0, |
| 122 | .f0 = PCI_DEV(0, 0x18, 0), |
| 123 | .f1 = PCI_DEV(0, 0x18, 1), |
| 124 | .f2 = PCI_DEV(0, 0x18, 2), |
| 125 | .f3 = PCI_DEV(0, 0x18, 3), |
| 126 | .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 }, |
| 127 | .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 }, |
| 128 | }, |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 129 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 130 | { |
| 131 | .node_id = 1, |
| 132 | .f0 = PCI_DEV(0, 0x19, 0), |
| 133 | .f1 = PCI_DEV(0, 0x19, 1), |
| 134 | .f2 = PCI_DEV(0, 0x19, 2), |
| 135 | .f3 = PCI_DEV(0, 0x19, 3), |
| 136 | .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 }, |
| 137 | .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 }, |
| 138 | |
| 139 | }, |
| 140 | #endif |
| 141 | |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 142 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 143 | { |
| 144 | .node_id = 2, |
| 145 | .f0 = PCI_DEV(0, 0x1a, 0), |
| 146 | .f1 = PCI_DEV(0, 0x1a, 1), |
| 147 | .f2 = PCI_DEV(0, 0x1a, 2), |
| 148 | .f3 = PCI_DEV(0, 0x1a, 3), |
| 149 | .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 }, |
| 150 | .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 }, |
| 151 | |
| 152 | }, |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 153 | { |
| 154 | .node_id = 3, |
| 155 | .f0 = PCI_DEV(0, 0x1b, 0), |
| 156 | .f1 = PCI_DEV(0, 0x1b, 1), |
| 157 | .f2 = PCI_DEV(0, 0x1b, 2), |
| 158 | .f3 = PCI_DEV(0, 0x1b, 3), |
| 159 | .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 }, |
| 160 | .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 }, |
| 161 | |
| 162 | }, |
| 163 | #endif |
| 164 | }; |
| 165 | |
| 166 | int needs_reset; |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 167 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame^] | 168 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | 776b85b | 2010-03-18 16:18:58 +0000 | [diff] [blame] | 169 | /* Nothing special needs to be done to find bus 0 */ |
| 170 | /* Allow the HT devices to be found */ |
| 171 | |
| 172 | enumerate_ht_chain(); |
| 173 | |
| 174 | amd8111_enable_rom(); |
| 175 | } |
| 176 | |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 177 | if (bist == 0) { |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 178 | init_cpus(cpu_init_detectedx); |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 179 | } |
| 180 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 181 | w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 182 | uart_init(); |
| 183 | console_init(); |
| 184 | |
| 185 | /* Halt if there was a built in self test failure */ |
| 186 | report_bist_failure(bist); |
| 187 | |
| 188 | setup_s4880_resource_map(); |
| 189 | |
| 190 | needs_reset = setup_coherent_ht_domain(); |
| 191 | |
| 192 | #if CONFIG_LOGICAL_CPUS==1 |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 193 | // It is said that we should start core1 after all core0 launched |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 194 | start_other_cores(); |
| 195 | #endif |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 196 | // automatically set that for you, but you might meet tight space |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 197 | needs_reset |= ht_setup_chains_x(); |
| 198 | |
| 199 | if (needs_reset) { |
| 200 | print_info("ht reset -\r\n"); |
| 201 | soft_reset(); |
| 202 | } |
| 203 | |
| 204 | enable_smbus(); |
| 205 | |
| 206 | memreset_setup(); |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 207 | sdram_initialize(ARRAY_SIZE(cpu), cpu); |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 208 | |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 209 | post_cache_as_ram(); |
arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame] | 210 | } |