arch import user (historical) | 7dec0f9 | 2005-07-06 18:17:06 +0000 | [diff] [blame^] | 1 | #define ASSEMBLY 1 |
| 2 | #define __ROMCC__ |
| 3 | |
| 4 | #include <stdint.h> |
| 5 | #include <device/pci_def.h> |
| 6 | #include <arch/io.h> |
| 7 | #include <device/pnp_def.h> |
| 8 | #include <arch/romcc_io.h> |
| 9 | #include <cpu/x86/lapic.h> |
| 10 | #include "option_table.h" |
| 11 | #include "pc80/mc146818rtc_early.c" |
| 12 | #include "pc80/serial.c" |
| 13 | #include "arch/i386/lib/console.c" |
| 14 | #include "ram/ramtest.c" |
| 15 | |
| 16 | #include "northbridge/amd/amdk8/cpu_rev.c" |
| 17 | #define K8_HT_FREQ_1G_SUPPORT 0 |
| 18 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 19 | #include "southbridge/amd/amd8111/amd8111_early_smbus.c" |
| 20 | #include "northbridge/amd/amdk8/raminit.h" |
| 21 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 22 | #include "lib/delay.c" |
| 23 | |
| 24 | #if CONFIG_USE_INIT == 0 |
| 25 | #include "lib/memcpy.c" |
| 26 | #endif |
| 27 | |
| 28 | #include "cpu/x86/lapic/boot_cpu.c" |
| 29 | #include "northbridge/amd/amdk8/reset_test.c" |
| 30 | #include "northbridge/amd/amdk8/debug.c" |
| 31 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| 32 | |
| 33 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 34 | #include "cpu/x86/bist.h" |
| 35 | |
| 36 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 37 | |
| 38 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 39 | |
| 40 | /* Look up a which bus a given node/link combination is on. |
| 41 | * return 0 when we can't find the answer. |
| 42 | */ |
| 43 | static unsigned node_link_to_bus(unsigned node, unsigned link) |
| 44 | { |
| 45 | unsigned reg; |
| 46 | |
| 47 | for(reg = 0xE0; reg < 0xF0; reg += 0x04) { |
| 48 | unsigned config_map; |
| 49 | config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); |
| 50 | if ((config_map & 3) != 3) { |
| 51 | continue; |
| 52 | } |
| 53 | if ((((config_map >> 4) & 7) == node) && |
| 54 | (((config_map >> 8) & 3) == link)) |
| 55 | { |
| 56 | return (config_map >> 16) & 0xff; |
| 57 | } |
| 58 | } |
| 59 | return 0; |
| 60 | } |
| 61 | |
| 62 | static void hard_reset(void) |
| 63 | { |
| 64 | device_t dev; |
| 65 | |
| 66 | /* Find the device */ |
| 67 | dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3); |
| 68 | |
| 69 | set_bios_reset(); |
| 70 | |
| 71 | /* enable cf9 */ |
| 72 | pci_write_config8(dev, 0x41, 0xf1); |
| 73 | /* reset */ |
| 74 | outb(0x0e, 0x0cf9); |
| 75 | } |
| 76 | |
| 77 | static void soft_reset(void) |
| 78 | { |
| 79 | device_t dev; |
| 80 | |
| 81 | /* Find the device */ |
| 82 | dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0); |
| 83 | |
| 84 | set_bios_reset(); |
| 85 | pci_write_config8(dev, 0x47, 1); |
| 86 | } |
| 87 | |
| 88 | static void memreset_setup(void) |
| 89 | { |
| 90 | if (is_cpu_pre_c0()) { |
| 91 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 |
| 92 | } |
| 93 | else { |
| 94 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 |
| 95 | } |
| 96 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); |
| 97 | } |
| 98 | |
| 99 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 100 | { |
| 101 | if (is_cpu_pre_c0()) { |
| 102 | udelay(800); |
| 103 | outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 |
| 104 | udelay(90); |
| 105 | } |
| 106 | } |
| 107 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 108 | { |
| 109 | #define SMBUS_HUB 0x18 |
| 110 | int ret; |
| 111 | unsigned device=(ctrl->channel0[0])>>8; |
| 112 | smbus_write_byte(SMBUS_HUB, 0x01, device); |
| 113 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 114 | } |
| 115 | |
| 116 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 117 | { |
| 118 | return smbus_read_byte(device, address); |
| 119 | } |
| 120 | |
| 121 | #define K8_4RANK_DIMM_SUPPORT 1 |
| 122 | |
| 123 | #include "northbridge/amd/amdk8/raminit.c" |
| 124 | #if 0 |
| 125 | #define ENABLE_APIC_EXT_ID 1 |
| 126 | #define APIC_ID_OFFSET 0x10 |
| 127 | #define LIFT_BSP_APIC_ID 0 |
| 128 | #else |
| 129 | #define ENABLE_APIC_EXT_ID 0 |
| 130 | #endif |
| 131 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 132 | #include "sdram/generic_sdram.c" |
| 133 | |
| 134 | /* tyan does not want the default */ |
| 135 | #include "resourcemap.c" |
| 136 | |
| 137 | #if CONFIG_LOGICAL_CPUS==1 |
| 138 | #define SET_NB_CFG_54 1 |
| 139 | #include "cpu/amd/dualcore/dualcore.c" |
| 140 | #else |
| 141 | #include "cpu/amd/model_fxx/node_id.c" |
| 142 | #endif |
| 143 | #define FIRST_CPU 1 |
| 144 | #define SECOND_CPU 1 |
| 145 | |
| 146 | #define THIRD_CPU 1 |
| 147 | #define FOURTH_CPU 1 |
| 148 | |
| 149 | #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU) |
| 150 | |
| 151 | #define RC0 ((1<<2)<<8) |
| 152 | #define RC1 ((1<<1)<<8) |
| 153 | #define RC2 ((1<<4)<<8) |
| 154 | #define RC3 ((1<<3)<<8) |
| 155 | |
| 156 | #define DIMM0 0x50 |
| 157 | #define DIMM1 0x51 |
| 158 | #define DIMM2 0x52 |
| 159 | #define DIMM3 0x53 |
| 160 | |
| 161 | #include "cpu/amd/car/copy_and_run.c" |
| 162 | |
| 163 | #if USE_FALLBACK_IMAGE == 1 |
| 164 | |
| 165 | #include "southbridge/amd/amd8111/amd8111_enable_rom.c" |
| 166 | #include "northbridge/amd/amdk8/early_ht.c" |
| 167 | |
| 168 | void real_main(unsigned long bist); |
| 169 | |
| 170 | void amd64_main(unsigned long bist) |
| 171 | { |
| 172 | #if CONFIG_LOGICAL_CPUS==1 |
| 173 | struct node_core_id id; |
| 174 | #else |
| 175 | unsigned nodeid; |
| 176 | #endif |
| 177 | /* Make cerain my local apic is useable */ |
| 178 | // enable_lapic(); |
| 179 | |
| 180 | #if CONFIG_LOGICAL_CPUS==1 |
| 181 | id = get_node_core_id_x(); |
| 182 | /* Is this a cpu only reset? */ |
| 183 | if (cpu_init_detected(id.nodeid)) { |
| 184 | #else |
| 185 | // nodeid = lapicid(); |
| 186 | nodeid = get_node_id(); |
| 187 | /* Is this a cpu only reset? */ |
| 188 | if (cpu_init_detected(nodeid)) { |
| 189 | #endif |
| 190 | if (last_boot_normal()) { |
| 191 | goto normal_image; |
| 192 | } else { |
| 193 | goto cpu_reset; |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | /* Is this a secondary cpu? */ |
| 198 | if (!boot_cpu()) { |
| 199 | if (last_boot_normal()) { |
| 200 | goto normal_image; |
| 201 | } else { |
| 202 | goto fallback_image; |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | /* Nothing special needs to be done to find bus 0 */ |
| 207 | /* Allow the HT devices to be found */ |
| 208 | |
| 209 | enumerate_ht_chain(); |
| 210 | |
| 211 | /* Setup the ck804 */ |
| 212 | amd8111_enable_rom(); |
| 213 | |
| 214 | /* Is this a deliberate reset by the bios */ |
| 215 | if (bios_reset_detected() && last_boot_normal()) { |
| 216 | goto normal_image; |
| 217 | } |
| 218 | /* This is the primary cpu how should I boot? */ |
| 219 | else if (do_normal_boot()) { |
| 220 | goto normal_image; |
| 221 | } |
| 222 | else { |
| 223 | goto fallback_image; |
| 224 | } |
| 225 | normal_image: |
| 226 | __asm__ volatile ("jmp __normal_image" |
| 227 | : /* outputs */ |
| 228 | : "a" (bist) /* inputs */ |
| 229 | ); |
| 230 | cpu_reset: |
| 231 | #if 0 |
| 232 | //CPU reset will reset memtroller ??? |
| 233 | asm volatile ("jmp __cpu_reset" |
| 234 | : /* outputs */ |
| 235 | : "a"(bist) /* inputs */ |
| 236 | ); |
| 237 | #endif |
| 238 | |
| 239 | fallback_image: |
| 240 | real_main(bist); |
| 241 | } |
| 242 | void real_main(unsigned long bist) |
| 243 | #else |
| 244 | void amd64_main(unsigned long bist) |
| 245 | #endif |
| 246 | { |
| 247 | static const struct mem_controller cpu[] = { |
| 248 | #if FIRST_CPU |
| 249 | { |
| 250 | .node_id = 0, |
| 251 | .f0 = PCI_DEV(0, 0x18, 0), |
| 252 | .f1 = PCI_DEV(0, 0x18, 1), |
| 253 | .f2 = PCI_DEV(0, 0x18, 2), |
| 254 | .f3 = PCI_DEV(0, 0x18, 3), |
| 255 | .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 }, |
| 256 | .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 }, |
| 257 | }, |
| 258 | #endif |
| 259 | #if SECOND_CPU |
| 260 | { |
| 261 | .node_id = 1, |
| 262 | .f0 = PCI_DEV(0, 0x19, 0), |
| 263 | .f1 = PCI_DEV(0, 0x19, 1), |
| 264 | .f2 = PCI_DEV(0, 0x19, 2), |
| 265 | .f3 = PCI_DEV(0, 0x19, 3), |
| 266 | .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 }, |
| 267 | .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 }, |
| 268 | |
| 269 | }, |
| 270 | #endif |
| 271 | |
| 272 | #if THIRD_CPU |
| 273 | { |
| 274 | .node_id = 2, |
| 275 | .f0 = PCI_DEV(0, 0x1a, 0), |
| 276 | .f1 = PCI_DEV(0, 0x1a, 1), |
| 277 | .f2 = PCI_DEV(0, 0x1a, 2), |
| 278 | .f3 = PCI_DEV(0, 0x1a, 3), |
| 279 | .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 }, |
| 280 | .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 }, |
| 281 | |
| 282 | }, |
| 283 | #endif |
| 284 | #if FOURTH_CPU |
| 285 | { |
| 286 | .node_id = 3, |
| 287 | .f0 = PCI_DEV(0, 0x1b, 0), |
| 288 | .f1 = PCI_DEV(0, 0x1b, 1), |
| 289 | .f2 = PCI_DEV(0, 0x1b, 2), |
| 290 | .f3 = PCI_DEV(0, 0x1b, 3), |
| 291 | .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 }, |
| 292 | .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 }, |
| 293 | |
| 294 | }, |
| 295 | #endif |
| 296 | }; |
| 297 | |
| 298 | int needs_reset; |
| 299 | unsigned cpu_reset = 0; |
| 300 | |
| 301 | if (bist == 0) { |
| 302 | #if CONFIG_LOGICAL_CPUS==1 |
| 303 | struct node_core_id id; |
| 304 | #else |
| 305 | unsigned nodeid; |
| 306 | #endif |
| 307 | /* Skip this if there was a built in self test failure */ |
| 308 | // amd_early_mtrr_init(); # don't need, already done in cache_as_ram |
| 309 | |
| 310 | #if CONFIG_LOGICAL_CPUS==1 |
| 311 | set_apicid_cpuid_lo(); |
| 312 | id = get_node_core_id_x(); // that is initid |
| 313 | #if ENABLE_APIC_EXT_ID == 1 |
| 314 | if(id.coreid == 0) { |
| 315 | enable_apic_ext_id(id.nodeid); |
| 316 | } |
| 317 | #endif |
| 318 | #else |
| 319 | nodeid = get_node_id(); |
| 320 | #if ENABLE_APIC_EXT_ID == 1 |
| 321 | enable_apic_ext_id(nodeid); |
| 322 | #endif |
| 323 | #endif |
| 324 | |
| 325 | enable_lapic(); |
| 326 | init_timer(); |
| 327 | |
| 328 | |
| 329 | #if CONFIG_LOGICAL_CPUS==1 |
| 330 | #if ENABLE_APIC_EXT_ID == 1 |
| 331 | #if LIFT_BSP_APIC_ID == 0 |
| 332 | if( id.nodeid != 0 ) //all except cores in node0 |
| 333 | #endif |
| 334 | lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); |
| 335 | #endif |
| 336 | if(id.coreid == 0) { |
| 337 | if (cpu_init_detected(id.nodeid)) { |
| 338 | cpu_reset = 1; |
| 339 | goto cpu_reset_x; |
| 340 | } |
| 341 | distinguish_cpu_resets(id.nodeid); |
| 342 | } |
| 343 | #else |
| 344 | #if ENABLE_APIC_EXT_ID == 1 |
| 345 | #if LIFT_BSP_APIC_ID == 0 |
| 346 | if(nodeid != 0) |
| 347 | #endif |
| 348 | lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 |
| 349 | |
| 350 | #endif |
| 351 | if (cpu_init_detected(nodeid)) { |
| 352 | cpu_reset = 1; |
| 353 | goto cpu_reset_x; |
| 354 | } |
| 355 | distinguish_cpu_resets(nodeid); |
| 356 | #endif |
| 357 | |
| 358 | |
| 359 | if (!boot_cpu() |
| 360 | #if CONFIG_LOGICAL_CPUS==1 |
| 361 | || (id.coreid != 0) |
| 362 | #endif |
| 363 | ) { |
| 364 | // We need stop the CACHE as RAM for this CPU too |
| 365 | #include "cpu/amd/car/cache_as_ram_post.c" |
| 366 | stop_this_cpu(); // it will stop all cores except core0 of cpu0 |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | |
| 371 | w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); |
| 372 | uart_init(); |
| 373 | console_init(); |
| 374 | |
| 375 | /* Halt if there was a built in self test failure */ |
| 376 | report_bist_failure(bist); |
| 377 | |
| 378 | setup_s4880_resource_map(); |
| 379 | |
| 380 | needs_reset = setup_coherent_ht_domain(); |
| 381 | |
| 382 | #if CONFIG_LOGICAL_CPUS==1 |
| 383 | start_other_cores(); |
| 384 | #endif |
| 385 | |
| 386 | needs_reset |= ht_setup_chains_x(); |
| 387 | |
| 388 | if (needs_reset) { |
| 389 | print_info("ht reset -\r\n"); |
| 390 | soft_reset(); |
| 391 | } |
| 392 | |
| 393 | enable_smbus(); |
| 394 | |
| 395 | memreset_setup(); |
| 396 | sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); |
| 397 | |
| 398 | |
| 399 | #if 1 |
| 400 | { |
| 401 | /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ |
| 402 | unsigned v_esp; |
| 403 | __asm__ volatile ( |
| 404 | "movl %%esp, %0\n\t" |
| 405 | : "=a" (v_esp) |
| 406 | ); |
| 407 | #if CONFIG_USE_INIT |
| 408 | printk_debug("v_esp=%08x\r\n", v_esp); |
| 409 | #else |
| 410 | print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); |
| 411 | #endif |
| 412 | } |
| 413 | #endif |
| 414 | |
| 415 | #if 1 |
| 416 | |
| 417 | |
| 418 | cpu_reset_x: |
| 419 | |
| 420 | #if CONFIG_USE_INIT |
| 421 | printk_debug("cpu_reset = %08x\r\n",cpu_reset); |
| 422 | #else |
| 423 | print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); |
| 424 | #endif |
| 425 | |
| 426 | if(cpu_reset == 0) { |
| 427 | print_debug("Clearing initial memory region: "); |
| 428 | } |
| 429 | print_debug("No cache as ram now - "); |
| 430 | |
| 431 | /* store cpu_reset to ebx */ |
| 432 | __asm__ volatile ( |
| 433 | "movl %0, %%ebx\n\t" |
| 434 | ::"a" (cpu_reset) |
| 435 | ); |
| 436 | |
| 437 | if(cpu_reset==0) { |
| 438 | #define CLEAR_FIRST_1M_RAM 1 |
| 439 | #include "cpu/amd/car/cache_as_ram_post.c" |
| 440 | } |
| 441 | else { |
| 442 | #undef CLEAR_FIRST_1M_RAM |
| 443 | #include "cpu/amd/car/cache_as_ram_post.c" |
| 444 | } |
| 445 | |
| 446 | __asm__ volatile ( |
| 447 | /* set new esp */ /* before _RAMBASE */ |
| 448 | "subl %0, %%ebp\n\t" |
| 449 | "subl %0, %%esp\n\t" |
| 450 | ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) |
| 451 | ); |
| 452 | |
| 453 | { |
| 454 | unsigned new_cpu_reset; |
| 455 | |
| 456 | /* get back cpu_reset from ebx */ |
| 457 | __asm__ volatile ( |
| 458 | "movl %%ebx, %0\n\t" |
| 459 | :"=a" (new_cpu_reset) |
| 460 | ); |
| 461 | |
| 462 | print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/ |
| 463 | if(new_cpu_reset==0) { |
| 464 | print_debug("done\r\n"); |
| 465 | } else |
| 466 | { |
| 467 | print_debug("\r\n"); |
| 468 | } |
| 469 | |
| 470 | #if CONFIG_USE_INIT |
| 471 | printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset); |
| 472 | #else |
| 473 | print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); |
| 474 | #endif |
| 475 | /*copy and execute linuxbios_ram */ |
| 476 | copy_and_run(new_cpu_reset); |
| 477 | /* We will not return */ |
| 478 | } |
| 479 | #endif |
| 480 | |
| 481 | |
| 482 | print_debug("should not be here -\r\n"); |
| 483 | |
| 484 | } |