Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 1 | #ifndef CPU_X86_MTRR_H |
| 2 | #define CPU_X86_MTRR_H |
| 3 | |
Nico Huber | ca74f8f | 2018-06-01 21:57:54 +0200 | [diff] [blame] | 4 | #ifndef __ASSEMBLER__ |
| 5 | #include <cpu/x86/msr.h> |
| 6 | #include <arch/cpu.h> |
| 7 | #endif |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 8 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 9 | /* These are the region types */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 10 | #define MTRR_TYPE_UNCACHEABLE 0 |
| 11 | #define MTRR_TYPE_WRCOMB 1 |
| 12 | #define MTRR_TYPE_WRTHROUGH 4 |
| 13 | #define MTRR_TYPE_WRPROT 5 |
| 14 | #define MTRR_TYPE_WRBACK 6 |
| 15 | #define MTRR_NUM_TYPES 7 |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 16 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 17 | #define MTRR_CAP_MSR 0x0fe |
Lee Leahy | bfdf248 | 2015-06-18 10:55:19 -0700 | [diff] [blame] | 18 | |
Kyösti Mälkki | eadd251 | 2020-06-11 09:52:45 +0300 | [diff] [blame] | 19 | #define MTRR_CAP_PRMRR (1 << 12) |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 20 | #define MTRR_CAP_SMRR (1 << 11) |
| 21 | #define MTRR_CAP_WC (1 << 10) |
| 22 | #define MTRR_CAP_FIX (1 << 8) |
| 23 | #define MTRR_CAP_VCNT 0xff |
Lee Leahy | bfdf248 | 2015-06-18 10:55:19 -0700 | [diff] [blame] | 24 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 25 | #define MTRR_DEF_TYPE_MSR 0x2ff |
| 26 | #define MTRR_DEF_TYPE_MASK 0xff |
| 27 | #define MTRR_DEF_TYPE_EN (1 << 11) |
| 28 | #define MTRR_DEF_TYPE_FIX_EN (1 << 10) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 29 | |
Arthur Heymans | e750b38e | 2018-07-20 23:31:59 +0200 | [diff] [blame] | 30 | #define IA32_SMRR_PHYS_BASE 0x1f2 |
| 31 | #define IA32_SMRR_PHYS_MASK 0x1f3 |
Tim Wawrzynczak | 62669a2 | 2020-09-01 16:08:02 -0600 | [diff] [blame] | 32 | #define SMRR_PHYS_MASK_LOCK (1 << 10) |
Duncan Laurie | 7b67892 | 2012-01-09 22:05:18 -0800 | [diff] [blame] | 33 | |
Arthur Heymans | eaaa549 | 2020-10-28 19:30:36 +0100 | [diff] [blame] | 34 | /* Specific to model_6fx and model_1067x. |
| 35 | These are named MSR_SMRR_PHYSBASE in the SDM. */ |
| 36 | #define CORE2_SMRR_PHYS_BASE 0xa0 |
| 37 | #define CORE2_SMRR_PHYS_MASK 0xa1 |
Arthur Heymans | 06f818c | 2018-07-20 23:41:54 +0200 | [diff] [blame] | 38 | |
Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 39 | #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) |
| 40 | #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 41 | #define MTRR_PHYS_MASK_VALID (1 << 11) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 42 | |
Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 43 | #define NUM_FIXED_RANGES 88 |
| 44 | #define RANGES_PER_FIXED_MTRR 8 |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 45 | #define MTRR_FIX_64K_00000 0x250 |
| 46 | #define MTRR_FIX_16K_80000 0x258 |
| 47 | #define MTRR_FIX_16K_A0000 0x259 |
| 48 | #define MTRR_FIX_4K_C0000 0x268 |
| 49 | #define MTRR_FIX_4K_C8000 0x269 |
| 50 | #define MTRR_FIX_4K_D0000 0x26a |
| 51 | #define MTRR_FIX_4K_D8000 0x26b |
| 52 | #define MTRR_FIX_4K_E0000 0x26c |
| 53 | #define MTRR_FIX_4K_E8000 0x26d |
| 54 | #define MTRR_FIX_4K_F0000 0x26e |
| 55 | #define MTRR_FIX_4K_F8000 0x26f |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 56 | |
Arthur Heymans | 1cb9cd5 | 2019-11-28 16:05:08 +0100 | [diff] [blame] | 57 | #if !defined(__ASSEMBLER__) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 58 | |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 59 | #include <stdint.h> |
| 60 | #include <stddef.h> |
| 61 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 62 | /* |
| 63 | * The MTRR code has some side effects that the callers should be aware for. |
| 64 | * 1. The call sequence matters. x86_setup_mtrrs() calls |
| 65 | * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent |
| 66 | * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers |
| 67 | * want to call the components of x86_setup_mtrrs() because of other |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 68 | * requirements the ordering should still preserved. |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 69 | * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because |
| 70 | * of the nature of the global MTRR enable flag. Therefore, all direct |
| 71 | * or indirect callers of enable_fixed_mtrr() should ensure that the |
| 72 | * variable MTRR MSRs do not contain bad ranges. |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 73 | * |
| 74 | * Note that this function sets up MTRRs for addresses above 4GiB. |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 75 | */ |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 76 | void x86_setup_mtrrs(void); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 77 | /* |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 78 | * x86_setup_mtrrs_with_detect() does the same thing as x86_setup_mtrrs(), but |
| 79 | * it always dynamically detects the number of variable MTRRs available. |
| 80 | */ |
| 81 | void x86_setup_mtrrs_with_detect(void); |
Aaron Durbin | 1ebbb16 | 2020-05-28 10:17:34 -0600 | [diff] [blame] | 82 | void x86_setup_mtrrs_with_detect_no_above_4gb(void); |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 83 | /* |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 84 | * x86_setup_var_mtrrs() parameters: |
| 85 | * address_bits - number of physical address bits supported by cpu |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 86 | * above4gb - if set setup MTRRs for addresses above 4GiB else ignore |
| 87 | * memory ranges above 4GiB |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 88 | */ |
| 89 | void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); |
| 90 | void enable_fixed_mtrr(void); |
Marshall Dawson | c0dbeda | 2017-10-19 09:45:16 -0600 | [diff] [blame] | 91 | /* Unhide Rd/WrDram bits and allow modification for AMD. */ |
| 92 | void fixed_mtrrs_expose_amd_rwdram(void); |
| 93 | /* Hide Rd/WrDram bits and allow modification for AMD. */ |
| 94 | void fixed_mtrrs_hide_amd_rwdram(void); |
Maciej Pijanka | ea92185 | 2009-10-27 14:29:29 +0000 | [diff] [blame] | 95 | void x86_setup_fixed_mtrrs(void); |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 96 | /* Set up fixed MTRRs but do not enable them. */ |
| 97 | void x86_setup_fixed_mtrrs_no_enable(void); |
Kyösti Mälkki | 38a8fb0 | 2014-06-30 13:48:18 +0300 | [diff] [blame] | 98 | void x86_mtrr_check(void); |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 99 | |
| 100 | /* Insert a temporary MTRR range for the duration of coreboot's runtime. |
| 101 | * This function needs to be called after the first MTRR solution is derived. */ |
| 102 | void mtrr_use_temp_range(uintptr_t begin, size_t size, int type); |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 103 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 104 | static inline int get_var_mtrr_count(void) |
| 105 | { |
| 106 | return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT; |
| 107 | } |
| 108 | |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 109 | void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, |
| 110 | unsigned int type); |
Furquan Shaikh | 331ac1b | 2016-03-16 16:12:06 -0700 | [diff] [blame] | 111 | int get_free_var_mtrr(void); |
Raul E Rangel | 3ae3ff2 | 2020-04-27 15:47:18 -0600 | [diff] [blame] | 112 | void clear_all_var_mtrr(void); |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 113 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 114 | asmlinkage void display_mtrrs(void); |
| 115 | |
Aaron Durbin | fa5eded | 2020-05-28 21:21:49 -0600 | [diff] [blame] | 116 | struct var_mtrr_context { |
Arthur Heymans | 46b409d | 2021-05-14 13:19:43 +0200 | [diff] [blame] | 117 | uint32_t max_var_mtrrs; |
| 118 | uint32_t used_var_mtrrs; |
| 119 | struct { |
| 120 | msr_t base; |
| 121 | msr_t mask; |
| 122 | } mtrr[]; |
Aaron Durbin | fa5eded | 2020-05-28 21:21:49 -0600 | [diff] [blame] | 123 | }; |
| 124 | |
Arthur Heymans | 46b409d | 2021-05-14 13:19:43 +0200 | [diff] [blame] | 125 | void var_mtrr_context_init(struct var_mtrr_context *ctx); |
Aaron Durbin | fa5eded | 2020-05-28 21:21:49 -0600 | [diff] [blame] | 126 | int var_mtrr_set(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, int type); |
Arthur Heymans | 46b409d | 2021-05-14 13:19:43 +0200 | [diff] [blame] | 127 | void commit_mtrr_setup(const struct var_mtrr_context *ctx); |
| 128 | void postcar_mtrr_setup(void); |
Nico Huber | ca74f8f | 2018-06-01 21:57:54 +0200 | [diff] [blame] | 129 | |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 130 | /* fms: find most significant bit set, stolen from Linux Kernel Source. */ |
| 131 | static inline unsigned int fms(unsigned int x) |
| 132 | { |
Elyes HAOUAS | db6c3f2 | 2019-06-26 21:05:17 +0200 | [diff] [blame] | 133 | unsigned int r; |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 134 | |
| 135 | __asm__("bsrl %1,%0\n\t" |
Lee Leahy | 708fc27 | 2017-03-07 12:18:53 -0800 | [diff] [blame] | 136 | "jnz 1f\n\t" |
| 137 | "movl $0,%0\n" |
Aaron Durbin | f4258de | 2017-11-01 15:47:05 -0600 | [diff] [blame] | 138 | "1:" : "=r" (r) : "mr" (x)); |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 139 | return r; |
| 140 | } |
| 141 | |
| 142 | /* fls: find least significant bit set */ |
| 143 | static inline unsigned int fls(unsigned int x) |
| 144 | { |
Elyes HAOUAS | db6c3f2 | 2019-06-26 21:05:17 +0200 | [diff] [blame] | 145 | unsigned int r; |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 146 | |
| 147 | __asm__("bsfl %1,%0\n\t" |
Lee Leahy | 708fc27 | 2017-03-07 12:18:53 -0800 | [diff] [blame] | 148 | "jnz 1f\n\t" |
| 149 | "movl $32,%0\n" |
Aaron Durbin | f4258de | 2017-11-01 15:47:05 -0600 | [diff] [blame] | 150 | "1:" : "=r" (r) : "mr" (x)); |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 151 | return r; |
| 152 | } |
Arthur Heymans | 1cb9cd5 | 2019-11-28 16:05:08 +0100 | [diff] [blame] | 153 | #endif /* !defined(__ASSEMBLER__) */ |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 154 | |
Arthur Heymans | 1cb9cd5 | 2019-11-28 16:05:08 +0100 | [diff] [blame] | 155 | /* Align up/down to next power of 2, suitable for assembler |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 156 | too. Range of result 256kB to 128MB is good enough here. */ |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 157 | #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ |
| 158 | (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) |
| 159 | #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 160 | #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) |
| 161 | |
| 162 | /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ |
Nico Huber | 540a664 | 2019-02-10 20:14:57 +0100 | [diff] [blame] | 163 | #define _FROM_4G_TOP(x) ((0xffffffff - (x)) + 1) |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 164 | |
Elyes HAOUAS | 918535a | 2016-07-28 21:25:21 +0200 | [diff] [blame] | 165 | /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set |
Kyösti Mälkki | 65cc526 | 2016-06-19 20:38:41 +0300 | [diff] [blame] | 166 | * as write-back cacheable to speed up ramstage decompression. |
| 167 | * Note MTRR boundaries, must be power of two. |
| 168 | */ |
| 169 | #define CACHE_TMP_RAMTOP (16<<20) |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 170 | |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 171 | /* For ROM caching, generally, try to use the next power of 2. */ |
| 172 | #define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) |
| 173 | #define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE) |
| 174 | #if (OPTIMAL_CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || \ |
| 175 | (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) |
| 176 | # error "Optimal CACHE_ROM_SIZE can't be derived, _POW2_MASK needs refinement." |
| 177 | #endif |
| 178 | |
| 179 | /* Make sure it doesn't overlap CAR, though. If the gap between |
| 180 | CAR and 4GiB is too small, make it at most the size of this |
| 181 | gap. As we can't align up (might overlap again), align down |
| 182 | to get a power of 2 again, for a single MTRR. */ |
| 183 | #define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) |
| 184 | #if CAR_END > OPTIMAL_CACHE_ROM_BASE |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 185 | # define CAR_CACHE_ROM_SIZE _ALIGN_DOWN_POW2(_FROM_4G_TOP(CAR_END)) |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 186 | #else |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 187 | # define CAR_CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 188 | #endif |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 189 | #if ((CAR_CACHE_ROM_SIZE & (CAR_CACHE_ROM_SIZE - 1)) != 0) |
| 190 | # error "CAR CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement." |
| 191 | #endif |
| 192 | |
| 193 | /* Last but not least, most (if not all) chipsets have MMIO |
| 194 | between 0xfe000000 and 0xff000000, so limit to 16MiB. */ |
Nico Huber | b781680 | 2020-05-27 17:29:30 +0200 | [diff] [blame] | 195 | #if CAR_CACHE_ROM_SIZE >= 16 << 20 |
| 196 | # define CACHE_ROM_SIZE (16 << 20) |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 197 | #else |
| 198 | # define CACHE_ROM_SIZE CAR_CACHE_ROM_SIZE |
Kyösti Mälkki | 5458b9d | 2012-06-30 11:41:08 +0300 | [diff] [blame] | 199 | #endif |
| 200 | |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 201 | #define CACHE_ROM_BASE _FROM_4G_TOP(CACHE_ROM_SIZE) |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 202 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 203 | #endif /* CPU_X86_MTRR_H */ |