Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 2 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 3 | #ifndef _CIMX_SB800_CHIP_H_ |
| 4 | #define _CIMX_SB800_CHIP_H_ |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 5 | #include "fan.h" /* include for #defines used in devicetree.cb */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 6 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 7 | /* |
| 8 | * configuration set in mainboard/devicetree.cb |
| 9 | * boot_switch_sata_ide: |
| 10 | * 0 -set SATA as primary, PATA(IDE) as secondary. |
| 11 | * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, |
| 12 | * gpp_configuration - The configuration of General Purpose Port A/B/C/D |
| 13 | * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] |
| 14 | * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] |
| 15 | * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 16 | * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 17 | */ |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 18 | struct southbridge_amd_cimx_sb800_config |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 19 | { |
| 20 | u32 boot_switch_sata_ide : 1; |
Kyösti Mälkki | 0b87bb7 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 21 | u32 disconnect_pcib : 1; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 22 | u8 gpp_configuration; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 23 | |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 24 | /* |
| 25 | * SB800 IMC and fan control |
| 26 | */ |
| 27 | |
| 28 | u16 imc_port_address; |
| 29 | |
| 30 | u32 fan0_enabled : 1; |
| 31 | u32 fan1_enabled : 1; |
| 32 | u32 fan2_enabled : 1; |
| 33 | u32 fan3_enabled : 1; |
| 34 | u32 fan4_enabled : 1; |
| 35 | u32 imc_fan_zone0_enabled : 1; |
| 36 | u32 imc_fan_zone1_enabled : 1; |
| 37 | u32 imc_fan_zone2_enabled : 1; |
| 38 | u32 imc_fan_zone3_enabled : 1; |
| 39 | u32 imc_tempin0_enabled : 1; |
| 40 | u32 imc_tempin1_enabled : 1; |
| 41 | u32 imc_tempin2_enabled : 1; |
| 42 | u32 imc_tempin3_enabled : 1; |
| 43 | |
| 44 | union { |
| 45 | struct { |
| 46 | u8 fan0_control_reg_value; |
| 47 | u8 fan0_frequency_reg_value; |
| 48 | u8 fan0_low_duty_reg_value; |
| 49 | u8 fan0_med_duty_reg_value; |
| 50 | u8 fan0_multiplier_reg_value; |
| 51 | u8 fan0_low_temp_lo_reg_value; |
| 52 | u8 fan0_low_temp_hi_reg_value; |
| 53 | u8 fan0_med_temp_lo_reg_value; |
| 54 | u8 fan0_med_temp_hi_reg_value; |
| 55 | u8 fan0_high_temp_lo_reg_value; |
| 56 | u8 fan0_high_temp_hi_reg_value; |
| 57 | u8 fan0_linear_range_reg_value; |
| 58 | u8 fan0_linear_hold_reg_value; |
| 59 | }; |
| 60 | u8 fan0_config_vals[FAN_REGISTER_COUNT]; |
| 61 | }; |
| 62 | |
| 63 | union { |
| 64 | struct { |
| 65 | u8 fan1_control_reg_value; |
| 66 | u8 fan1_frequency_reg_value; |
| 67 | u8 fan1_low_duty_reg_value; |
| 68 | u8 fan1_med_duty_reg_value; |
| 69 | u8 fan1_multiplier_reg_value; |
| 70 | u8 fan1_low_temp_lo_reg_value; |
| 71 | u8 fan1_low_temp_hi_reg_value; |
| 72 | u8 fan1_med_temp_lo_reg_value; |
| 73 | u8 fan1_med_temp_hi_reg_value; |
| 74 | u8 fan1_high_temp_lo_reg_value; |
| 75 | u8 fan1_high_temp_hi_reg_value; |
| 76 | u8 fan1_linear_range_reg_value; |
| 77 | u8 fan1_linear_hold_reg_value; |
| 78 | }; |
| 79 | u8 fan1_config_vals[FAN_REGISTER_COUNT]; |
| 80 | }; |
| 81 | |
| 82 | union { |
| 83 | struct { |
| 84 | u8 fan2_control_reg_value; |
| 85 | u8 fan2_frequency_reg_value; |
| 86 | u8 fan2_low_duty_reg_value; |
| 87 | u8 fan2_med_duty_reg_value; |
| 88 | u8 fan2_multiplier_reg_value; |
| 89 | u8 fan2_low_temp_lo_reg_value; |
| 90 | u8 fan2_low_temp_hi_reg_value; |
| 91 | u8 fan2_med_temp_lo_reg_value; |
| 92 | u8 fan2_med_temp_hi_reg_value; |
| 93 | u8 fan2_high_temp_lo_reg_value; |
| 94 | u8 fan2_high_temp_hi_reg_value; |
| 95 | u8 fan2_linear_range_reg_value; |
| 96 | u8 fan2_linear_hold_reg_value; |
| 97 | }; |
| 98 | u8 fan2_config_vals[FAN_REGISTER_COUNT]; |
| 99 | }; |
| 100 | |
| 101 | union { |
| 102 | struct { |
| 103 | u8 fan3_control_reg_value; |
| 104 | u8 fan3_frequency_reg_value; |
| 105 | u8 fan3_low_duty_reg_value; |
| 106 | u8 fan3_med_duty_reg_value; |
| 107 | u8 fan3_multiplier_reg_value; |
| 108 | u8 fan3_low_temp_lo_reg_value; |
| 109 | u8 fan3_low_temp_hi_reg_value; |
| 110 | u8 fan3_med_temp_lo_reg_value; |
| 111 | u8 fan3_med_temp_hi_reg_value; |
| 112 | u8 fan3_high_temp_lo_reg_value; |
| 113 | u8 fan3_high_temp_hi_reg_value; |
| 114 | u8 fan3_linear_range_reg_value; |
| 115 | u8 fan3_linear_hold_reg_value; |
| 116 | }; |
| 117 | u8 fan3_config_vals[FAN_REGISTER_COUNT]; |
| 118 | }; |
| 119 | |
| 120 | union { |
| 121 | struct { |
| 122 | u8 fan4_control_reg_value; |
| 123 | u8 fan4_frequency_reg_value; |
| 124 | u8 fan4_low_duty_reg_value; |
| 125 | u8 fan4_med_duty_reg_value; |
| 126 | u8 fan4_multiplier_reg_value; |
| 127 | u8 fan4_low_temp_lo_reg_value; |
| 128 | u8 fan4_low_temp_hi_reg_value; |
| 129 | u8 fan4_med_temp_lo_reg_value; |
| 130 | u8 fan4_med_temp_hi_reg_value; |
| 131 | u8 fan4_high_temp_lo_reg_value; |
| 132 | u8 fan4_high_temp_hi_reg_value; |
| 133 | u8 fan4_linear_range_reg_value; |
| 134 | u8 fan4_linear_hold_reg_value; |
| 135 | }; |
| 136 | u8 fan4_config_vals[FAN_REGISTER_COUNT]; |
| 137 | }; |
| 138 | |
| 139 | union { |
| 140 | struct { |
| 141 | u8 imc_zone0_mode1; |
| 142 | u8 imc_zone0_mode2; |
| 143 | u8 imc_zone0_temp_offset; |
| 144 | u8 imc_zone0_hysteresis; |
| 145 | u8 imc_zone0_smbus_addr; |
| 146 | u8 imc_zone0_smbus_num; |
| 147 | u8 imc_zone0_pwm_step; |
| 148 | u8 imc_zone0_ramping; |
| 149 | }; |
| 150 | u8 imc_zone0_config_vals[IMC_FAN_CONFIG_COUNT]; |
| 151 | }; |
| 152 | u8 imc_zone0_thresholds[IMC_FAN_THRESHOLD_COUNT]; |
| 153 | u8 imc_zone0_fanspeeds[IMC_FAN_SPEED_COUNT]; |
| 154 | |
| 155 | union { |
| 156 | struct { |
| 157 | u8 imc_zone1_mode1; |
| 158 | u8 imc_zone1_mode2; |
| 159 | u8 imc_zone1_temp_offset; |
| 160 | u8 imc_zone1_hysteresis; |
| 161 | u8 imc_zone1_smbus_addr; |
| 162 | u8 imc_zone1_smbus_num; |
| 163 | u8 imc_zone1_pwm_step; |
| 164 | u8 imc_zone1_ramping; |
| 165 | }; |
| 166 | u8 imc_zone1_config_vals[IMC_FAN_CONFIG_COUNT]; |
| 167 | }; |
| 168 | u8 imc_zone1_thresholds[IMC_FAN_THRESHOLD_COUNT]; |
| 169 | u8 imc_zone1_fanspeeds[IMC_FAN_SPEED_COUNT]; |
| 170 | |
| 171 | union { |
| 172 | struct { |
| 173 | u8 imc_zone2_mode1; |
| 174 | u8 imc_zone2_mode2; |
| 175 | u8 imc_zone2_temp_offset; |
| 176 | u8 imc_zone2_hysteresis; |
| 177 | u8 imc_zone2_smbus_addr; |
| 178 | u8 imc_zone2_smbus_num; |
| 179 | u8 imc_zone2_pwm_step; |
| 180 | u8 imc_zone2_ramping; |
| 181 | }; |
| 182 | u8 imc_zone2_config_vals[IMC_FAN_CONFIG_COUNT]; |
| 183 | }; |
| 184 | u8 imc_zone2_thresholds[IMC_FAN_THRESHOLD_COUNT]; |
| 185 | u8 imc_zone2_fanspeeds[IMC_FAN_SPEED_COUNT]; |
| 186 | |
| 187 | union { |
| 188 | struct { |
| 189 | u8 imc_zone3_mode1; |
| 190 | u8 imc_zone3_mode2; |
| 191 | u8 imc_zone3_temp_offset; |
| 192 | u8 imc_zone3_hysteresis; |
| 193 | u8 imc_zone3_smbus_addr; |
| 194 | u8 imc_zone3_smbus_num; |
| 195 | u8 imc_zone3_pwm_step; |
| 196 | u8 imc_zone3_ramping; |
| 197 | }; |
| 198 | u8 imc_zone3_config_vals[IMC_FAN_CONFIG_COUNT]; |
| 199 | }; |
| 200 | u8 imc_zone3_thresholds[IMC_FAN_THRESHOLD_COUNT]; |
| 201 | u8 imc_zone3_fanspeeds[IMC_FAN_SPEED_COUNT]; |
| 202 | |
| 203 | u32 imc_tempin0_at; |
| 204 | u32 imc_tempin0_ct; |
| 205 | u8 imc_tempin0_tuning_param; |
| 206 | |
| 207 | u32 imc_tempin1_at; |
| 208 | u32 imc_tempin1_ct; |
| 209 | u8 imc_tempin1_tuning_param; |
| 210 | |
| 211 | u32 imc_tempin2_at; |
| 212 | u32 imc_tempin2_ct; |
| 213 | u8 imc_tempin2_tuning_param; |
| 214 | |
| 215 | u32 imc_tempin3_at; |
| 216 | u32 imc_tempin3_ct; |
| 217 | u8 imc_tempin3_tuning_param; |
| 218 | |
| 219 | }; |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 220 | #endif /* _CIMX_SB800_CHIP_H_ */ |