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review.coreboot.org / coreboot / 182dbdeac4b2489f8d03a47a79ab28ad556d9d21 / . / src / southbridge / amd / cimx / sb800 / chip.h
blob: bb4b2dbf1510651e19d72993e2e52c1179166bb4 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]3
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]4#ifndef _CIMX_SB800_CHIP_H_
5#define _CIMX_SB800_CHIP_H_
Martin Rothe899e512012-12-05 16:07:11 -0700[diff] [blame]6#include "fan.h" /* include for #defines used in devicetree.cb */
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]7
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]8/*
9 * configuration set in mainboard/devicetree.cb
10 * boot_switch_sata_ide:
11 * 0 -set SATA as primary, PATA(IDE) as secondary.
12 * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
13 * gpp_configuration - The configuration of General Purpose Port A/B/C/D
14 * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
15 * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
16 * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
17 * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
18 */
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]19struct southbridge_amd_cimx_sb800_config
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]20{
21 u32 boot_switch_sata_ide : 1;
Kyösti Mälkki0b87bb72014-11-11 17:22:23 +0200[diff] [blame]22 u32 disconnect_pcib : 1;
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]23 u8 gpp_configuration;
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]24
Martin Rothe899e512012-12-05 16:07:11 -0700[diff] [blame]25 /*
26 * SB800 IMC and fan control
27 */
28
29 u16 imc_port_address;
30
31 u32 fan0_enabled : 1;
32 u32 fan1_enabled : 1;
33 u32 fan2_enabled : 1;
34 u32 fan3_enabled : 1;
35 u32 fan4_enabled : 1;
36 u32 imc_fan_zone0_enabled : 1;
37 u32 imc_fan_zone1_enabled : 1;
38 u32 imc_fan_zone2_enabled : 1;
39 u32 imc_fan_zone3_enabled : 1;
40 u32 imc_tempin0_enabled : 1;
41 u32 imc_tempin1_enabled : 1;
42 u32 imc_tempin2_enabled : 1;
43 u32 imc_tempin3_enabled : 1;
44
45 union {
46 struct {
47 u8 fan0_control_reg_value;
48 u8 fan0_frequency_reg_value;
49 u8 fan0_low_duty_reg_value;
50 u8 fan0_med_duty_reg_value;
51 u8 fan0_multiplier_reg_value;
52 u8 fan0_low_temp_lo_reg_value;
53 u8 fan0_low_temp_hi_reg_value;
54 u8 fan0_med_temp_lo_reg_value;
55 u8 fan0_med_temp_hi_reg_value;
56 u8 fan0_high_temp_lo_reg_value;
57 u8 fan0_high_temp_hi_reg_value;
58 u8 fan0_linear_range_reg_value;
59 u8 fan0_linear_hold_reg_value;
60 };
61 u8 fan0_config_vals[FAN_REGISTER_COUNT];
62 };
63
64 union {
65 struct {
66 u8 fan1_control_reg_value;
67 u8 fan1_frequency_reg_value;
68 u8 fan1_low_duty_reg_value;
69 u8 fan1_med_duty_reg_value;
70 u8 fan1_multiplier_reg_value;
71 u8 fan1_low_temp_lo_reg_value;
72 u8 fan1_low_temp_hi_reg_value;
73 u8 fan1_med_temp_lo_reg_value;
74 u8 fan1_med_temp_hi_reg_value;
75 u8 fan1_high_temp_lo_reg_value;
76 u8 fan1_high_temp_hi_reg_value;
77 u8 fan1_linear_range_reg_value;
78 u8 fan1_linear_hold_reg_value;
79 };
80 u8 fan1_config_vals[FAN_REGISTER_COUNT];
81 };
82
83 union {
84 struct {
85 u8 fan2_control_reg_value;
86 u8 fan2_frequency_reg_value;
87 u8 fan2_low_duty_reg_value;
88 u8 fan2_med_duty_reg_value;
89 u8 fan2_multiplier_reg_value;
90 u8 fan2_low_temp_lo_reg_value;
91 u8 fan2_low_temp_hi_reg_value;
92 u8 fan2_med_temp_lo_reg_value;
93 u8 fan2_med_temp_hi_reg_value;
94 u8 fan2_high_temp_lo_reg_value;
95 u8 fan2_high_temp_hi_reg_value;
96 u8 fan2_linear_range_reg_value;
97 u8 fan2_linear_hold_reg_value;
98 };
99 u8 fan2_config_vals[FAN_REGISTER_COUNT];
100 };
101
102 union {
103 struct {
104 u8 fan3_control_reg_value;
105 u8 fan3_frequency_reg_value;
106 u8 fan3_low_duty_reg_value;
107 u8 fan3_med_duty_reg_value;
108 u8 fan3_multiplier_reg_value;
109 u8 fan3_low_temp_lo_reg_value;
110 u8 fan3_low_temp_hi_reg_value;
111 u8 fan3_med_temp_lo_reg_value;
112 u8 fan3_med_temp_hi_reg_value;
113 u8 fan3_high_temp_lo_reg_value;
114 u8 fan3_high_temp_hi_reg_value;
115 u8 fan3_linear_range_reg_value;
116 u8 fan3_linear_hold_reg_value;
117 };
118 u8 fan3_config_vals[FAN_REGISTER_COUNT];
119 };
120
121 union {
122 struct {
123 u8 fan4_control_reg_value;
124 u8 fan4_frequency_reg_value;
125 u8 fan4_low_duty_reg_value;
126 u8 fan4_med_duty_reg_value;
127 u8 fan4_multiplier_reg_value;
128 u8 fan4_low_temp_lo_reg_value;
129 u8 fan4_low_temp_hi_reg_value;
130 u8 fan4_med_temp_lo_reg_value;
131 u8 fan4_med_temp_hi_reg_value;
132 u8 fan4_high_temp_lo_reg_value;
133 u8 fan4_high_temp_hi_reg_value;
134 u8 fan4_linear_range_reg_value;
135 u8 fan4_linear_hold_reg_value;
136 };
137 u8 fan4_config_vals[FAN_REGISTER_COUNT];
138 };
139
140 union {
141 struct {
142 u8 imc_zone0_mode1;
143 u8 imc_zone0_mode2;
144 u8 imc_zone0_temp_offset;
145 u8 imc_zone0_hysteresis;
146 u8 imc_zone0_smbus_addr;
147 u8 imc_zone0_smbus_num;
148 u8 imc_zone0_pwm_step;
149 u8 imc_zone0_ramping;
150 };
151 u8 imc_zone0_config_vals[IMC_FAN_CONFIG_COUNT];
152 };
153 u8 imc_zone0_thresholds[IMC_FAN_THRESHOLD_COUNT];
154 u8 imc_zone0_fanspeeds[IMC_FAN_SPEED_COUNT];
155
156 union {
157 struct {
158 u8 imc_zone1_mode1;
159 u8 imc_zone1_mode2;
160 u8 imc_zone1_temp_offset;
161 u8 imc_zone1_hysteresis;
162 u8 imc_zone1_smbus_addr;
163 u8 imc_zone1_smbus_num;
164 u8 imc_zone1_pwm_step;
165 u8 imc_zone1_ramping;
166 };
167 u8 imc_zone1_config_vals[IMC_FAN_CONFIG_COUNT];
168 };
169 u8 imc_zone1_thresholds[IMC_FAN_THRESHOLD_COUNT];
170 u8 imc_zone1_fanspeeds[IMC_FAN_SPEED_COUNT];
171
172 union {
173 struct {
174 u8 imc_zone2_mode1;
175 u8 imc_zone2_mode2;
176 u8 imc_zone2_temp_offset;
177 u8 imc_zone2_hysteresis;
178 u8 imc_zone2_smbus_addr;
179 u8 imc_zone2_smbus_num;
180 u8 imc_zone2_pwm_step;
181 u8 imc_zone2_ramping;
182 };
183 u8 imc_zone2_config_vals[IMC_FAN_CONFIG_COUNT];
184 };
185 u8 imc_zone2_thresholds[IMC_FAN_THRESHOLD_COUNT];
186 u8 imc_zone2_fanspeeds[IMC_FAN_SPEED_COUNT];
187
188 union {
189 struct {
190 u8 imc_zone3_mode1;
191 u8 imc_zone3_mode2;
192 u8 imc_zone3_temp_offset;
193 u8 imc_zone3_hysteresis;
194 u8 imc_zone3_smbus_addr;
195 u8 imc_zone3_smbus_num;
196 u8 imc_zone3_pwm_step;
197 u8 imc_zone3_ramping;
198 };
199 u8 imc_zone3_config_vals[IMC_FAN_CONFIG_COUNT];
200 };
201 u8 imc_zone3_thresholds[IMC_FAN_THRESHOLD_COUNT];
202 u8 imc_zone3_fanspeeds[IMC_FAN_SPEED_COUNT];
203
204 u32 imc_tempin0_at;
205 u32 imc_tempin0_ct;
206 u8 imc_tempin0_tuning_param;
207
208 u32 imc_tempin1_at;
209 u32 imc_tempin1_ct;
210 u8 imc_tempin1_tuning_param;
211
212 u32 imc_tempin2_at;
213 u32 imc_tempin2_ct;
214 u8 imc_tempin2_tuning_param;
215
216 u32 imc_tempin3_at;
217 u32 imc_tempin3_ct;
218 u8 imc_tempin3_tuning_param;
219
220};
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]221#endif /* _CIMX_SB800_CHIP_H_ */