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Rex-BC Chen73e6b8e2021-11-02 10:31:53 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2
Rex-BC Chen362a4812021-12-02 19:17:06 +08003#include <bootmem.h>
Rex-BC Chen73e6b8e2021-11-02 10:31:53 +08004#include <device/device.h>
Runyang Chena0583a42021-12-19 21:15:03 +08005#include <soc/devapc.h>
Rex-BC Chen362a4812021-12-02 19:17:06 +08006#include <soc/dfd.h>
Rex-BC Chen73e6b8e2021-11-02 10:31:53 +08007#include <soc/emi.h>
Rex-BC Chenf8eed652021-11-11 15:50:42 +08008#include <soc/mmu_operations.h>
Rex-BC Chend8e8c872021-11-08 14:28:54 +08009#include <soc/sspm.h>
Rex-BC Chen73e6b8e2021-11-02 10:31:53 +080010#include <symbols.h>
11
Rex-BC Chen362a4812021-12-02 19:17:06 +080012void bootmem_platform_add_ranges(void)
13{
14 if (CONFIG(MTK_DFD))
15 bootmem_add_range(DFD_DUMP_ADDRESS, DFD_DUMP_SIZE, BM_MEM_RESERVED);
16}
17
Rex-BC Chen73e6b8e2021-11-02 10:31:53 +080018static void soc_read_resources(struct device *dev)
19{
Kyösti Mälkki27d62992022-05-24 20:25:58 +030020 ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
Rex-BC Chen73e6b8e2021-11-02 10:31:53 +080021}
22
23static void soc_init(struct device *dev)
24{
Rex-BC Chenf8eed652021-11-11 15:50:42 +080025 mtk_mmu_disable_l2c_sram();
Rex-BC Chend8e8c872021-11-08 14:28:54 +080026 sspm_init();
Runyang Chena0583a42021-12-19 21:15:03 +080027 dapc_init();
Rex-BC Chen362a4812021-12-02 19:17:06 +080028
29 if (CONFIG(MTK_DFD))
30 dfd_init();
Rex-BC Chen73e6b8e2021-11-02 10:31:53 +080031}
32
33static struct device_operations soc_ops = {
34 .read_resources = soc_read_resources,
Yu-Ping Wu39e6f852022-03-14 16:53:59 +080035 .set_resources = noop_set_resources,
Rex-BC Chen73e6b8e2021-11-02 10:31:53 +080036 .init = soc_init,
37};
38
39static void enable_soc_dev(struct device *dev)
40{
41 dev->ops = &soc_ops;
42}
43
44struct chip_operations soc_mediatek_mt8186_ops = {
45 CHIP_NAME("SOC Mediatek MT8186")
46 .enable_dev = enable_soc_dev,
47};