Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <drivers/i2c/designware/dw_i2c.h> |
| 7 | #include <intelblocks/cfg.h> |
| 8 | #include <intelblocks/gpio.h> |
| 9 | #include <intelblocks/gspi.h> |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 10 | #include <intelblocks/pcie_rp.h> |
Sumeet R Pawnikar | e8d1bef | 2020-05-08 21:31:44 +0530 | [diff] [blame] | 11 | #include <intelblocks/power_limit.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 12 | #include <soc/gpe.h> |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 13 | #include <soc/gpio.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 14 | #include <soc/pch.h> |
| 15 | #include <soc/pci_devs.h> |
Jamie Chen | 1ebcb2a | 2021-07-20 18:33:57 +0800 | [diff] [blame] | 16 | #include <soc/pcie_modphy.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 17 | #include <soc/pmc.h> |
| 18 | #include <soc/serialio.h> |
| 19 | #include <soc/usb.h> |
| 20 | #include <stdint.h> |
| 21 | |
| 22 | #define MAX_HD_AUDIO_DMIC_LINKS 2 |
| 23 | #define MAX_HD_AUDIO_SNDW_LINKS 4 |
| 24 | #define MAX_HD_AUDIO_SSP_LINKS 6 |
| 25 | |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 26 | struct soc_intel_jasperlake_config { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 27 | |
| 28 | /* Common struct containing soc config data required by common code */ |
| 29 | struct soc_intel_common_config common_soc_config; |
| 30 | |
Sumeet R Pawnikar | e8d1bef | 2020-05-08 21:31:44 +0530 | [diff] [blame] | 31 | /* Common struct containing power limits configuration information */ |
| 32 | struct soc_power_limits_config power_limits_config; |
| 33 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 34 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 35 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 36 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 37 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 38 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 39 | |
| 40 | /* Generic IO decode ranges */ |
| 41 | uint32_t gen1_dec; |
| 42 | uint32_t gen2_dec; |
| 43 | uint32_t gen3_dec; |
| 44 | uint32_t gen4_dec; |
| 45 | |
| 46 | /* Enable S0iX support */ |
| 47 | int s0ix_enable; |
| 48 | /* Enable DPTF support */ |
| 49 | int dptf_enable; |
| 50 | |
| 51 | /* Deep SX enable for both AC and DC */ |
| 52 | int deep_s3_enable_ac; |
| 53 | int deep_s3_enable_dc; |
| 54 | int deep_s5_enable_ac; |
| 55 | int deep_s5_enable_dc; |
| 56 | |
| 57 | /* Deep Sx Configuration |
| 58 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 59 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 60 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 61 | uint32_t deep_sx_config; |
| 62 | |
| 63 | /* TCC activation offset */ |
| 64 | uint32_t tcc_offset; |
| 65 | |
Aamir Bohra | e9984c8 | 2020-09-09 14:28:45 +0530 | [diff] [blame] | 66 | /* System Agent dynamic frequency support. |
| 67 | * When enabled memory will be training at different frequencies. |
| 68 | * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 |
| 69 | * (high), 4:Enabled */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 70 | enum { |
| 71 | SaGv_Disabled, |
| 72 | SaGv_FixedPoint0, |
| 73 | SaGv_FixedPoint1, |
| 74 | SaGv_FixedPoint2, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 75 | SaGv_Enabled, |
| 76 | } SaGv; |
| 77 | |
| 78 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 79 | uint8_t RMT; |
| 80 | |
| 81 | /* USB related */ |
| 82 | struct usb2_port_config usb2_ports[16]; |
| 83 | struct usb3_port_config usb3_ports[10]; |
| 84 | /* Wake Enable Bitmap for USB2 ports */ |
| 85 | uint16_t usb2_wake_enable_bitmap; |
| 86 | /* Wake Enable Bitmap for USB3 ports */ |
| 87 | uint16_t usb3_wake_enable_bitmap; |
| 88 | |
Ben Kao | 6eb5253 | 2021-07-04 21:24:36 +0800 | [diff] [blame] | 89 | /* Set the LFPS periodic sampling off time for USB3 Ports. |
| 90 | Default value of PMCTRL_REG bits[7:4] is 9 which means periodic |
| 91 | sampling off interval is 9ms, the range is from 0 to 15. */ |
| 92 | uint8_t xhci_lfps_sampling_offtime_ms; |
| 93 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 94 | /* SATA related */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 95 | uint8_t SataMode; |
| 96 | uint8_t SataSalpSupport; |
| 97 | uint8_t SataPortsEnable[8]; |
| 98 | uint8_t SataPortsDevSlp[8]; |
| 99 | |
| 100 | /* Audio related */ |
| 101 | uint8_t PchHdaDspEnable; |
| 102 | uint8_t PchHdaAudioLinkHdaEnable; |
| 103 | uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; |
| 104 | uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; |
| 105 | uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; |
| 106 | uint8_t PchHdaIDispLinkTmode; |
| 107 | uint8_t PchHdaIDispLinkFrequency; |
| 108 | uint8_t PchHdaIDispCodecDisconnect; |
| 109 | |
| 110 | /* PCIe Root Ports */ |
| 111 | uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
| 112 | /* PCIe output clocks type to PCIe devices. |
| 113 | * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, |
| 114 | * 0xFF: not used */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 115 | uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 116 | /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to |
| 117 | * clksrc. */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 118 | uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 119 | |
Meera Ravindranath | 798fd4b | 2020-04-27 22:40:03 +0530 | [diff] [blame] | 120 | /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ |
| 121 | uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; |
| 122 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 123 | /* PCIe RP L1 substate */ |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 124 | enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 125 | |
Jamie Chen | 1ebcb2a | 2021-07-20 18:33:57 +0800 | [diff] [blame] | 126 | /* PCIe ModPhy related */ |
| 127 | struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS]; |
| 128 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 129 | /* SMBus */ |
| 130 | uint8_t SmbusEnable; |
| 131 | |
| 132 | /* eMMC and SD */ |
| 133 | uint8_t ScsEmmcHs400Enabled; |
| 134 | |
| 135 | /* Enable if SD Card Power Enable Signal is Active High */ |
| 136 | uint8_t SdCardPowerEnableActiveHigh; |
| 137 | |
Meera Ravindranath | 5b3a0ff | 2020-09-23 12:43:43 +0530 | [diff] [blame] | 138 | /* VR Config Settings for IA Core */ |
| 139 | uint16_t ImonSlope; |
| 140 | uint16_t ImonOffset; |
| 141 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 142 | /* Gfx related */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 143 | uint8_t SkipExtGfxScan; |
| 144 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 145 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 146 | uint8_t eist_enable; |
| 147 | |
| 148 | /* Enable C6 DRAM */ |
| 149 | uint8_t enable_c6dram; |
Michael Niewöhner | 0e25580 | 2021-09-15 12:58:11 +0200 | [diff] [blame] | 150 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 151 | /* |
| 152 | * SerialIO device mode selection: |
| 153 | * PchSerialIoDisabled, |
| 154 | * PchSerialIoPci, |
| 155 | * PchSerialIoHidden, |
| 156 | * PchSerialIoLegacyUart, |
| 157 | * PchSerialIoSkipInit |
| 158 | */ |
| 159 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 160 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 161 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 162 | /* |
| 163 | * GSPIn Default Chip Select Mode: |
| 164 | * 0:Hardware Mode, |
| 165 | * 1:Software Mode |
| 166 | */ |
| 167 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 168 | /* |
| 169 | * GSPIn Default Chip Select State: |
| 170 | * 0: Low, |
| 171 | * 1: High |
| 172 | */ |
| 173 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 174 | |
| 175 | /* |
| 176 | * TraceHubMode config |
| 177 | * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode |
| 178 | */ |
| 179 | uint8_t TraceHubMode; |
| 180 | |
| 181 | /* Debug interface selection */ |
| 182 | enum { |
| 183 | DEBUG_INTERFACE_RAM = (1 << 0), |
Subrata Banik | 7be0df8 | 2020-04-30 12:23:16 +0530 | [diff] [blame] | 184 | DEBUG_INTERFACE_UART_8250IO = (1 << 1), |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 185 | DEBUG_INTERFACE_USB3 = (1 << 3), |
Subrata Banik | 7be0df8 | 2020-04-30 12:23:16 +0530 | [diff] [blame] | 186 | DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 187 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 188 | } debug_interface_flag; |
| 189 | |
| 190 | /* GPIO SD card detect pin */ |
| 191 | unsigned int sdcard_cd_gpio; |
| 192 | |
| 193 | /* Enable Pch iSCLK */ |
| 194 | uint8_t pch_isclk; |
| 195 | |
| 196 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
Angel Pons | 98521c5 | 2021-03-01 21:16:49 +0100 | [diff] [blame] | 197 | bool CnviBtAudioOffload; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 198 | |
| 199 | /* Tcss */ |
| 200 | uint8_t TcssXhciEn; |
| 201 | uint8_t TcssXdciEn; |
| 202 | |
| 203 | /* |
| 204 | * Override GPIO PM configuration: |
| 205 | * 0: Use FSP default GPIO PM program, |
| 206 | * 1: coreboot to override GPIO PM program |
| 207 | */ |
| 208 | uint8_t gpio_override_pm; |
| 209 | |
| 210 | /* |
| 211 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 212 | * Bit 6-7: Reserved |
| 213 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 214 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 215 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 216 | * Bit 2: MISCCFG_GSXLCGEN |
| 217 | * Bit 1: MISCCFG_GPDPCGEN |
| 218 | * Bit 0: MISCCFG_GPDLCGEN |
| 219 | */ |
| 220 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 221 | |
| 222 | /* DP config */ |
| 223 | /* |
| 224 | * Port config |
| 225 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 226 | */ |
| 227 | uint8_t DdiPortAConfig; |
| 228 | uint8_t DdiPortBConfig; |
| 229 | |
| 230 | /* Enable(1)/Disable(0) HPD */ |
| 231 | uint8_t DdiPortAHpd; |
| 232 | uint8_t DdiPortBHpd; |
| 233 | uint8_t DdiPortCHpd; |
| 234 | uint8_t DdiPort1Hpd; |
| 235 | uint8_t DdiPort2Hpd; |
| 236 | uint8_t DdiPort3Hpd; |
| 237 | uint8_t DdiPort4Hpd; |
| 238 | |
| 239 | /* Enable(1)/Disable(0) DDC */ |
| 240 | uint8_t DdiPortADdc; |
| 241 | uint8_t DdiPortBDdc; |
| 242 | uint8_t DdiPortCDdc; |
| 243 | uint8_t DdiPort1Ddc; |
| 244 | uint8_t DdiPort2Ddc; |
| 245 | uint8_t DdiPort3Ddc; |
| 246 | uint8_t DdiPort4Ddc; |
| 247 | |
| 248 | /* Hybrid storage mode enable (1) / disable (0) |
| 249 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 250 | * accordingly */ |
| 251 | uint8_t HybridStorageMode; |
| 252 | |
| 253 | /* |
| 254 | * Override CPU flex ratio value: |
| 255 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 256 | * Valid Range 0 to 63. |
| 257 | * In general descriptor provides option to set default cpu flex ratio. |
| 258 | * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. |
| 259 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 260 | * Only override CPU flex ratio to not boot with non-turbo max. |
| 261 | */ |
| 262 | uint8_t cpu_ratio_override; |
| 263 | |
V Sowmya | e8156ad | 2020-06-17 16:17:19 +0530 | [diff] [blame] | 264 | /* Skip CPU replacement check |
| 265 | * 0: disable |
| 266 | * 1: enable |
| 267 | * Setting this option to skip CPU replacement check to avoid the forced MRC training |
| 268 | * for the platforms with soldered down SOC. |
| 269 | */ |
| 270 | uint8_t SkipCpuReplacementCheck; |
V Sowmya | 7aee5c6 | 2020-07-24 08:58:14 +0530 | [diff] [blame] | 271 | |
| 272 | /* |
| 273 | * SLP_S3 Minimum Assertion Width Policy |
| 274 | * 1 = 60us |
| 275 | * 2 = 1ms |
| 276 | * 3 = 50ms (default) |
| 277 | * 4 = 2s |
| 278 | */ |
| 279 | uint8_t PchPmSlpS3MinAssert; |
| 280 | |
| 281 | /* |
| 282 | * SLP_S4 Minimum Assertion Width Policy |
| 283 | * 1 = 1s (default) |
| 284 | * 2 = 2s |
| 285 | * 3 = 3s |
| 286 | * 4 = 4s |
| 287 | */ |
| 288 | uint8_t PchPmSlpS4MinAssert; |
| 289 | |
| 290 | /* |
| 291 | * SLP_SUS Minimum Assertion Width Policy |
| 292 | * 1 = 0ms |
| 293 | * 2 = 500ms |
| 294 | * 3 = 1s |
| 295 | * 4 = 4s (default) |
| 296 | */ |
| 297 | uint8_t PchPmSlpSusMinAssert; |
| 298 | |
| 299 | /* |
| 300 | * SLP_A Minimum Assertion Width Policy |
| 301 | * 1 = 0ms |
| 302 | * 2 = 4s |
| 303 | * 3 = 98ms |
| 304 | * 4 = 2s (default) |
| 305 | */ |
| 306 | uint8_t PchPmSlpAMinAssert; |
| 307 | |
| 308 | /* |
| 309 | * PCH PM Reset Power Cycle Duration |
| 310 | * 0 = 4s (default) |
| 311 | * 1 = 1s |
| 312 | * 2 = 2s |
| 313 | * 3 = 3s |
| 314 | * 4 = 4s |
| 315 | * |
| 316 | * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the |
| 317 | * stretch duration programmed in the following registers: |
| 318 | * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 319 | * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 320 | * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 321 | * - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 322 | */ |
| 323 | uint8_t PchPmPwrCycDur; |
Maulik V Vaghela | 58ce447 | 2020-11-06 10:56:57 +0530 | [diff] [blame] | 324 | |
| 325 | /* |
| 326 | * FIVR RFI Frequency |
| 327 | * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. |
| 328 | * 0: Auto. |
| 329 | * Range varies based on XTAL clock: |
| 330 | * 0-1918 (Up to 191.8HMz) for 24MHz clock; |
| 331 | * 0-1535 (Up to 153.5MHz) for 19MHz clock. |
| 332 | */ |
| 333 | uint16_t FivrRfiFrequency; |
| 334 | |
| 335 | /* |
| 336 | * FIVR RFI Spread Spectrum |
| 337 | * Set the Spread Spectrum Range. <b>0: 0%</b>; |
| 338 | * FIVR RFI Spread Spectrum, in 0.1% increments. |
| 339 | * Range: 0.0% to 10.0% (0-100) |
| 340 | */ |
| 341 | uint8_t FivrSpreadSpectrum; |
Maulik V Vaghela | a4bef79 | 2020-11-23 20:42:39 +0530 | [diff] [blame] | 342 | |
| 343 | /* |
Maulik V Vaghela | 2e424ff | 2021-01-06 22:04:37 +0530 | [diff] [blame] | 344 | * Disable Fast Slew Rate for Deep Package C States for VCCIN VR domain |
Maulik V Vaghela | a4bef79 | 2020-11-23 20:42:39 +0530 | [diff] [blame] | 345 | * Disable Fast Slew Rate for Deep Package C States based on |
| 346 | * Acoustic Noise Mitigation feature enabled. |
| 347 | */ |
| 348 | uint8_t FastPkgCRampDisable; |
| 349 | |
| 350 | /* |
Maulik V Vaghela | 2e424ff | 2021-01-06 22:04:37 +0530 | [diff] [blame] | 351 | * Slew Rate configuration for Deep Package C States for VCCIN VR domain |
Maulik V Vaghela | a4bef79 | 2020-11-23 20:42:39 +0530 | [diff] [blame] | 352 | * based on Acoustic Noise Mitigation feature enabled. |
| 353 | * 0: Fast/2 ; 1: Fast/4; 2: Fast/8; 3: Fast/16 |
| 354 | */ |
Maulik V Vaghela | 2e424ff | 2021-01-06 22:04:37 +0530 | [diff] [blame] | 355 | enum { |
| 356 | SlewRateFastBy2 = 0, |
| 357 | SlewRateFastBy4, |
| 358 | SlewRateFastBy8, |
| 359 | SlewRateFastBy16 |
| 360 | } SlowSlewRate; |
Maulik V Vaghela | a4bef79 | 2020-11-23 20:42:39 +0530 | [diff] [blame] | 361 | |
| 362 | /* |
| 363 | * Enable or Disable Acoustic Noise Mitigation feature. |
| 364 | * 0: Disabled ; 1: Enabled |
| 365 | */ |
| 366 | uint8_t AcousticNoiseMitigation; |
| 367 | |
| 368 | /* |
| 369 | * Acoustic Noise Mitigation Range.Defines the maximum Pre-Wake |
| 370 | * randomization time in micro ticks.This can be programmed only |
| 371 | * if AcousticNoiseMitigation is enabled. |
| 372 | * Range 0-255 |
| 373 | */ |
| 374 | uint8_t PreWake; |
| 375 | |
| 376 | /* |
| 377 | * Acoustic Noise Mitigation Range.Defines the maximum Ramp Up |
| 378 | * randomization time in micro ticks.This can be programmed only |
| 379 | * if AcousticNoiseMitigation is enabled. |
| 380 | * Range 0-255 |
| 381 | */ |
| 382 | uint8_t RampUp; |
| 383 | |
| 384 | /* |
| 385 | * Acoustic Noise Mitigation Range.Defines the maximum Ramp Down |
| 386 | * randomization time in micro ticks.This can be programmed only |
| 387 | * if AcousticNoiseMitigation is enabled. |
| 388 | * Range 0-255 |
| 389 | */ |
| 390 | uint8_t RampDown; |
| 391 | |
Simon Yang | df52085 | 2021-06-22 10:15:20 +0800 | [diff] [blame] | 392 | /* |
| 393 | * It controls below soc variables |
| 394 | * |
| 395 | * PchFivrExtV1p05RailEnabledStates |
| 396 | * PchFivrExtVnnRailSxEnabledStates |
| 397 | * PchFivrExtVnnRailEnabledStates |
| 398 | * |
| 399 | * If your platform does not support external vnn power rail please set to 1 |
| 400 | * 1: Disabled ; 0: Enabled |
| 401 | */ |
| 402 | bool disable_external_bypass_vr; |
| 403 | |
Simon Yang | 355fb2f | 2021-12-09 19:42:24 +0800 | [diff] [blame] | 404 | /* |
| 405 | * Core Display Clock Frequency selection, FSP UPD CdClock values + 1 |
| 406 | * |
| 407 | * FSP will use the value to program clock frequency for core display if GOP |
| 408 | * is not run. Ex: the Chromebook normal mode. |
| 409 | * For the cases GOP is run, GOP will be in charge of the related register |
| 410 | * settings. |
| 411 | */ |
| 412 | enum { |
| 413 | CD_CLOCK_172_8_MHZ = 1, |
| 414 | CD_CLOCK_180_MHZ = 2, |
| 415 | CD_CLOCK_192_MHZ = 3, |
| 416 | CD_CLOCK_307_MHZ = 4, |
| 417 | CD_CLOCK_312_MHZ = 5, |
| 418 | CD_CLOCK_552_MHZ = 6, |
| 419 | CD_CLOCK_556_8_MHZ = 7, |
Simon Yang | 355fb2f | 2021-12-09 19:42:24 +0800 | [diff] [blame] | 420 | } cd_clock; |
| 421 | |
Jamie Chen | 5b58902 | 2022-03-15 16:16:30 +0800 | [diff] [blame] | 422 | /* |
| 423 | * This is a workaround to mitigate higher SoC power consumption in S0ix |
| 424 | * when the CNVI has background activity. |
| 425 | * |
| 426 | * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in |
| 427 | * cppmvric1 register to 0) will break CNVI timing. |
| 428 | * Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and |
| 429 | * AX201 (HrP2) |
| 430 | * |
| 431 | * true: Enabled (fewer wakes, lower power) |
| 432 | * false: Disabled (more wakes, higher power) |
| 433 | */ |
| 434 | bool cnvi_reduce_s0ix_pwr_usage; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 435 | }; |
| 436 | |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 437 | typedef struct soc_intel_jasperlake_config config_t; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 438 | |
| 439 | #endif |