Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | |
| 4 | #ifndef _SOC_CHIP_H_ |
| 5 | #define _SOC_CHIP_H_ |
| 6 | |
| 7 | #include <drivers/i2c/designware/dw_i2c.h> |
| 8 | #include <intelblocks/cfg.h> |
| 9 | #include <intelblocks/gpio.h> |
| 10 | #include <intelblocks/gspi.h> |
| 11 | #include <soc/gpe.h> |
| 12 | #include <soc/gpio.h> |
| 13 | #include <soc/gpio_defs.h> |
| 14 | #include <soc/pch.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pmc.h> |
| 17 | #include <soc/serialio.h> |
| 18 | #include <soc/usb.h> |
| 19 | #include <stdint.h> |
| 20 | |
| 21 | #define MAX_HD_AUDIO_DMIC_LINKS 2 |
| 22 | #define MAX_HD_AUDIO_SNDW_LINKS 4 |
| 23 | #define MAX_HD_AUDIO_SSP_LINKS 6 |
| 24 | |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 25 | struct soc_intel_jasperlake_config { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 26 | |
| 27 | /* Common struct containing soc config data required by common code */ |
| 28 | struct soc_intel_common_config common_soc_config; |
| 29 | |
| 30 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 31 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 32 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 33 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 34 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 35 | |
| 36 | /* Generic IO decode ranges */ |
| 37 | uint32_t gen1_dec; |
| 38 | uint32_t gen2_dec; |
| 39 | uint32_t gen3_dec; |
| 40 | uint32_t gen4_dec; |
| 41 | |
| 42 | /* Enable S0iX support */ |
| 43 | int s0ix_enable; |
| 44 | /* Enable DPTF support */ |
| 45 | int dptf_enable; |
| 46 | |
| 47 | /* Deep SX enable for both AC and DC */ |
| 48 | int deep_s3_enable_ac; |
| 49 | int deep_s3_enable_dc; |
| 50 | int deep_s5_enable_ac; |
| 51 | int deep_s5_enable_dc; |
| 52 | |
| 53 | /* Deep Sx Configuration |
| 54 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 55 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 56 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 57 | uint32_t deep_sx_config; |
| 58 | |
| 59 | /* TCC activation offset */ |
| 60 | uint32_t tcc_offset; |
| 61 | |
| 62 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
| 63 | * When enabled memory will be training at two different frequencies. |
| 64 | * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, |
| 65 | * 4:FixedPoint3, 5:Enabled */ |
| 66 | enum { |
| 67 | SaGv_Disabled, |
| 68 | SaGv_FixedPoint0, |
| 69 | SaGv_FixedPoint1, |
| 70 | SaGv_FixedPoint2, |
| 71 | SaGv_FixedPoint3, |
| 72 | SaGv_Enabled, |
| 73 | } SaGv; |
| 74 | |
| 75 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 76 | uint8_t RMT; |
| 77 | |
| 78 | /* USB related */ |
| 79 | struct usb2_port_config usb2_ports[16]; |
| 80 | struct usb3_port_config usb3_ports[10]; |
| 81 | /* Wake Enable Bitmap for USB2 ports */ |
| 82 | uint16_t usb2_wake_enable_bitmap; |
| 83 | /* Wake Enable Bitmap for USB3 ports */ |
| 84 | uint16_t usb3_wake_enable_bitmap; |
| 85 | |
| 86 | /* SATA related */ |
| 87 | uint8_t SataEnable; |
| 88 | uint8_t SataMode; |
| 89 | uint8_t SataSalpSupport; |
| 90 | uint8_t SataPortsEnable[8]; |
| 91 | uint8_t SataPortsDevSlp[8]; |
| 92 | |
| 93 | /* Audio related */ |
| 94 | uint8_t PchHdaDspEnable; |
| 95 | uint8_t PchHdaAudioLinkHdaEnable; |
| 96 | uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; |
| 97 | uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; |
| 98 | uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; |
| 99 | uint8_t PchHdaIDispLinkTmode; |
| 100 | uint8_t PchHdaIDispLinkFrequency; |
| 101 | uint8_t PchHdaIDispCodecDisconnect; |
| 102 | |
| 103 | /* PCIe Root Ports */ |
| 104 | uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
| 105 | /* PCIe output clocks type to PCIe devices. |
| 106 | * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, |
| 107 | * 0xFF: not used */ |
| 108 | uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; |
| 109 | /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to |
| 110 | * clksrc. */ |
| 111 | uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; |
| 112 | |
Meera Ravindranath | 798fd4b | 2020-04-27 22:40:03 +0530 | [diff] [blame^] | 113 | /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ |
| 114 | uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; |
| 115 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 116 | /* PCIe RP L1 substate */ |
| 117 | enum L1_substates_control { |
| 118 | L1_SS_FSP_DEFAULT, |
| 119 | L1_SS_DISABLED, |
| 120 | L1_SS_L1_1, |
| 121 | L1_SS_L1_2, |
| 122 | } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; |
| 123 | |
| 124 | /* SMBus */ |
| 125 | uint8_t SmbusEnable; |
| 126 | |
| 127 | /* eMMC and SD */ |
| 128 | uint8_t ScsEmmcHs400Enabled; |
| 129 | |
| 130 | /* Enable if SD Card Power Enable Signal is Active High */ |
| 131 | uint8_t SdCardPowerEnableActiveHigh; |
| 132 | |
| 133 | /* Integrated Sensor */ |
| 134 | uint8_t PchIshEnable; |
| 135 | |
| 136 | /* Heci related */ |
| 137 | uint8_t Heci3Enabled; |
| 138 | |
| 139 | /* Gfx related */ |
| 140 | uint8_t IgdDvmt50PreAlloc; |
| 141 | uint8_t InternalGfx; |
| 142 | uint8_t SkipExtGfxScan; |
| 143 | |
| 144 | uint32_t GraphicsConfigPtr; |
| 145 | uint8_t Device4Enable; |
| 146 | |
| 147 | /* HeciEnabled decides the state of Heci1 at end of boot |
| 148 | * Setting to 0 (default) disables Heci1 and hides the device from OS */ |
| 149 | uint8_t HeciEnabled; |
| 150 | /* PL2 Override value in Watts */ |
| 151 | uint32_t tdp_pl2_override; |
| 152 | /* Intel Speed Shift Technology */ |
| 153 | uint8_t speed_shift_enable; |
| 154 | |
| 155 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 156 | uint8_t eist_enable; |
| 157 | |
| 158 | /* Enable C6 DRAM */ |
| 159 | uint8_t enable_c6dram; |
| 160 | /* |
| 161 | * PRMRR size setting with below options |
| 162 | * Disable: 0x0 |
| 163 | * 32MB: 0x2000000 |
| 164 | * 64MB: 0x4000000 |
| 165 | * 128 MB: 0x8000000 |
| 166 | * 256 MB: 0x10000000 |
| 167 | * 512 MB: 0x20000000 |
| 168 | */ |
| 169 | uint32_t PrmrrSize; |
| 170 | uint8_t PmTimerDisabled; |
| 171 | /* |
| 172 | * SerialIO device mode selection: |
| 173 | * PchSerialIoDisabled, |
| 174 | * PchSerialIoPci, |
| 175 | * PchSerialIoHidden, |
| 176 | * PchSerialIoLegacyUart, |
| 177 | * PchSerialIoSkipInit |
| 178 | */ |
| 179 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 180 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 181 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 182 | /* |
| 183 | * GSPIn Default Chip Select Mode: |
| 184 | * 0:Hardware Mode, |
| 185 | * 1:Software Mode |
| 186 | */ |
| 187 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 188 | /* |
| 189 | * GSPIn Default Chip Select State: |
| 190 | * 0: Low, |
| 191 | * 1: High |
| 192 | */ |
| 193 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 194 | |
| 195 | /* |
| 196 | * TraceHubMode config |
| 197 | * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode |
| 198 | */ |
| 199 | uint8_t TraceHubMode; |
| 200 | |
| 201 | /* Debug interface selection */ |
| 202 | enum { |
| 203 | DEBUG_INTERFACE_RAM = (1 << 0), |
| 204 | DEBUG_INTERFACE_UART = (1 << 1), |
| 205 | DEBUG_INTERFACE_USB3 = (1 << 3), |
| 206 | DEBUG_INTERFACE_SERIAL_IO = (1 << 4), |
| 207 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 208 | } debug_interface_flag; |
| 209 | |
| 210 | /* GPIO SD card detect pin */ |
| 211 | unsigned int sdcard_cd_gpio; |
| 212 | |
| 213 | /* Enable Pch iSCLK */ |
| 214 | uint8_t pch_isclk; |
| 215 | |
| 216 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
| 217 | enum { |
| 218 | FORCE_DISABLE, |
| 219 | FORCE_ENABLE, |
| 220 | } CnviBtAudioOffload; |
| 221 | |
| 222 | /* Tcss */ |
| 223 | uint8_t TcssXhciEn; |
| 224 | uint8_t TcssXdciEn; |
| 225 | |
| 226 | /* |
| 227 | * Override GPIO PM configuration: |
| 228 | * 0: Use FSP default GPIO PM program, |
| 229 | * 1: coreboot to override GPIO PM program |
| 230 | */ |
| 231 | uint8_t gpio_override_pm; |
| 232 | |
| 233 | /* |
| 234 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 235 | * Bit 6-7: Reserved |
| 236 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 237 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 238 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 239 | * Bit 2: MISCCFG_GSXLCGEN |
| 240 | * Bit 1: MISCCFG_GPDPCGEN |
| 241 | * Bit 0: MISCCFG_GPDLCGEN |
| 242 | */ |
| 243 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 244 | |
| 245 | /* DP config */ |
| 246 | /* |
| 247 | * Port config |
| 248 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 249 | */ |
| 250 | uint8_t DdiPortAConfig; |
| 251 | uint8_t DdiPortBConfig; |
| 252 | |
| 253 | /* Enable(1)/Disable(0) HPD */ |
| 254 | uint8_t DdiPortAHpd; |
| 255 | uint8_t DdiPortBHpd; |
| 256 | uint8_t DdiPortCHpd; |
| 257 | uint8_t DdiPort1Hpd; |
| 258 | uint8_t DdiPort2Hpd; |
| 259 | uint8_t DdiPort3Hpd; |
| 260 | uint8_t DdiPort4Hpd; |
| 261 | |
| 262 | /* Enable(1)/Disable(0) DDC */ |
| 263 | uint8_t DdiPortADdc; |
| 264 | uint8_t DdiPortBDdc; |
| 265 | uint8_t DdiPortCDdc; |
| 266 | uint8_t DdiPort1Ddc; |
| 267 | uint8_t DdiPort2Ddc; |
| 268 | uint8_t DdiPort3Ddc; |
| 269 | uint8_t DdiPort4Ddc; |
| 270 | |
| 271 | /* Hybrid storage mode enable (1) / disable (0) |
| 272 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 273 | * accordingly */ |
| 274 | uint8_t HybridStorageMode; |
| 275 | |
| 276 | /* |
| 277 | * Override CPU flex ratio value: |
| 278 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 279 | * Valid Range 0 to 63. |
| 280 | * In general descriptor provides option to set default cpu flex ratio. |
| 281 | * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. |
| 282 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 283 | * Only override CPU flex ratio to not boot with non-turbo max. |
| 284 | */ |
| 285 | uint8_t cpu_ratio_override; |
| 286 | |
| 287 | }; |
| 288 | |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 289 | typedef struct soc_intel_jasperlake_config config_t; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 290 | |
| 291 | #endif |