blob: 594b256fec63b1c6ab41bc93caa15befbcabe108 [file] [log] [blame]
Angel Pons585495e2020-04-03 01:21:38 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Gerd Hoffmannee941b382013-06-07 16:03:44 +02002
3#include <device/device.h>
4#include <device/pci.h>
Gerd Hoffmannee941b382013-06-07 16:03:44 +02005#include <device/pci_ops.h>
6#include <pc80/keyboard.h>
Patrick Rudolphd12f0302021-02-03 17:33:40 +01007#include <cpu/x86/smm.h>
Gerd Hoffmannee941b382013-06-07 16:03:44 +02008
Angel Pons816a41c2021-01-28 11:09:56 +01009#include "q35.h"
Gerd Hoffmannee941b382013-06-07 16:03:44 +020010
11static const unsigned char qemu_q35_irqs[] = {
12 10, 10, 11, 11,
13 10, 10, 11, 11,
14};
15
Elyes HAOUAS5cb876c2018-06-08 18:31:43 +020016static void qemu_nb_init(struct device *dev)
Gerd Hoffmannee941b382013-06-07 16:03:44 +020017{
18 /* Map memory at 0xc0000 - 0xfffff */
19 int i;
Angel Pons816a41c2021-01-28 11:09:56 +010020 uint8_t v = pci_read_config8(dev, D0F0_PAM(0));
Gerd Hoffmannee941b382013-06-07 16:03:44 +020021 v |= 0x30;
Angel Pons816a41c2021-01-28 11:09:56 +010022 pci_write_config8(dev, D0F0_PAM(0), v);
23 pci_write_config8(dev, D0F0_PAM(1), 0x33);
24 pci_write_config8(dev, D0F0_PAM(2), 0x33);
25 pci_write_config8(dev, D0F0_PAM(3), 0x33);
26 pci_write_config8(dev, D0F0_PAM(4), 0x33);
27 pci_write_config8(dev, D0F0_PAM(5), 0x33);
28 pci_write_config8(dev, D0F0_PAM(6), 0x33);
Gerd Hoffmannee941b382013-06-07 16:03:44 +020029
Paul Menzelfeecdc22020-06-20 23:01:37 +020030 /* This sneaked in here, because Qemu does not emulate a SuperIO chip. */
Timothy Pearson448e3862015-11-24 14:12:01 -060031 pc_keyboard_init(NO_AUX_DEVICE);
Gerd Hoffmannee941b382013-06-07 16:03:44 +020032
33 /* setup IRQ routing for pci slots */
Angel Ponsc76c59a2021-06-28 14:00:57 +020034 for (i = 0; i < 25; i++) {
35 struct device *d = pcidev_on_root(i, 0);
36 if (d)
37 pci_assign_irqs(d, qemu_q35_irqs + (i % 4));
38 }
Gerd Hoffmannee941b382013-06-07 16:03:44 +020039 /* setup IRQ routing southbridge devices */
Angel Ponsc76c59a2021-06-28 14:00:57 +020040 for (i = 25; i < 32; i++) {
41 struct device *d = pcidev_on_root(i, 0);
42 if (d)
43 pci_assign_irqs(d, qemu_q35_irqs);
44 }
Gerd Hoffmannee941b382013-06-07 16:03:44 +020045}
46
47static void qemu_nb_read_resources(struct device *dev)
48{
Patrick Rudolphd12f0302021-02-03 17:33:40 +010049 size_t tseg_size;
50 uintptr_t tseg_base;
51
Gerd Hoffmannee941b382013-06-07 16:03:44 +020052 pci_dev_read_resources(dev);
53
Angel Ponscba669c2021-01-28 11:56:45 +010054 mmconf_resource(dev, 2);
Patrick Rudolph82e111c2021-01-07 14:12:38 +010055
56 if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
57 /* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
Kyösti Mälkki27d62992022-05-24 20:25:58 +030058 reserved_ram_resource_kb(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB,
Patrick Rudolph82e111c2021-01-07 14:12:38 +010059 (6 * 0x1000) / KiB);
60 }
Patrick Rudolphd12f0302021-02-03 17:33:40 +010061
62 smm_region(&tseg_base, &tseg_size);
Kyösti Mälkki27d62992022-05-24 20:25:58 +030063 reserved_ram_resource_kb(dev, ESMRAMC, tseg_base / 1024, tseg_size / 1024);
Gerd Hoffmannee941b382013-06-07 16:03:44 +020064}
65
66
67static struct device_operations nb_operations = {
68 .read_resources = qemu_nb_read_resources,
69 .set_resources = pci_dev_set_resources,
70 .enable_resources = pci_dev_enable_resources,
71 .init = qemu_nb_init,
Gerd Hoffmannee941b382013-06-07 16:03:44 +020072};
73
74static const struct pci_driver nb_driver __pci_driver = {
75 .ops = &nb_operations,
76 .vendor = 0x8086,
77 .device = 0x29c0,
78};