blob: 9703cdb2da72d1aa852b5734d073ab9448860f65 [file] [log] [blame]
Lee Leahyc4210412015-06-29 11:37:56 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
14 * GNU General Public License for more details.
Lee Leahyc4210412015-06-29 11:37:56 -070015 */
16
robbie zhangc9d97292015-08-21 09:47:34 -070017#ifndef MAINBOARD_GPIO_H
18#define MAINBOARD_GPIO_H
Lee Leahyc4210412015-06-29 11:37:56 -070019
Wenkai Du3b169252015-08-24 10:31:30 -070020#include <soc/gpe.h>
Lee Leahyc4210412015-06-29 11:37:56 -070021#include <soc/gpio.h>
22
Wenkai Du3b169252015-08-24 10:31:30 -070023/* EC in RW */
24#define GPIO_EC_IN_RW GPP_C6
25
26/* BIOS Flash Write Protect */
27#define GPIO_PCH_WP GPP_C23
Duncan Laurie74b964e2015-09-04 10:41:02 -070028
29/* Memory configuration board straps */
30#define GPIO_MEM_CONFIG_0 GPP_C12
31#define GPIO_MEM_CONFIG_1 GPP_C13
32#define GPIO_MEM_CONFIG_2 GPP_C14
33#define GPIO_MEM_CONFIG_3 GPP_C15
34
Wenkai Du3b169252015-08-24 10:31:30 -070035/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
36#define GPE_EC_WAKE GPE0_LAN_WAK
Duncan Laurie74b964e2015-09-04 10:41:02 -070037
Duncan Lauried6a42f92015-09-08 16:28:21 -070038/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
39#define GPE_WLAN_WAKE GPE0_DW0_16
40
Archana Patni278f20e2015-11-05 18:38:03 +053041/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
42#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
43
Duncan Laurie74b964e2015-09-04 10:41:02 -070044/* Input device interrupt configuration */
45#define TOUCHPAD_INT_L GPP_B3_IRQ
46#define TOUCHSCREEN_INT_L GPP_E7_IRQ
47#define MIC_INT_L GPP_F10_IRQ
48
Duncan Lauried6a42f92015-09-08 16:28:21 -070049/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
Wenkai Du3b169252015-08-24 10:31:30 -070050#define EC_SCI_GPI GPE0_DW2_16
51#define EC_SMI_GPI GPP_E15
52
53#ifndef __ACPI__
Wenkai Du1105fad2015-08-21 13:11:00 -070054/* Pad configuration in ramstage. */
robbie zhangc9d97292015-08-21 09:47:34 -070055static const struct pad_config gpio_table[] = {
56/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
57/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
58/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
59/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
60/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
61/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
62/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
63/* PIRQA# */ /* GPP_A7 */
64/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
65/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
66/* PCH_LPC_CLK */ /* GPP_A10 */
67/* EC_HID_INT */ /* GPP_A11 */
68/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 0, DEEP),
69/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
70/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
71/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
72/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
73/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
74/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
75/* ISH_GP1 */ /* GPP_A19 */
76/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
77/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
78/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
79/* ISH_GP5 */ /* GPP_A23 */
80/* CORE_VID0 */ /* GPP_B0 */
81/* CORE_VID1 */ /* GPP_B1 */
82/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
83/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP),
84/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
Archana Patni278f20e2015-11-05 18:38:03 +053085/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
robbie zhangc9d97292015-08-21 09:47:34 -070086/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
87/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
88/* SRCCLKREQ3# */ /* GPP_B8 */
89/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
90/* SRCCLKREQ5# */ /* GPP_B10 */
91/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
92/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
93/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
94/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
95/* GSPI0_CS# */ /* GPP_B15 */
Duncan Lauried6a42f92015-09-08 16:28:21 -070096/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
robbie zhangc9d97292015-08-21 09:47:34 -070097/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
98/* GSPI0_MOSI */ /* GPP_B18 */
99/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
100/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
101/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
102/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
Archana Patni7d40e962015-10-08 01:42:07 +0530103/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),
robbie zhangc9d97292015-08-21 09:47:34 -0700104/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
105/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
106/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
107/* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP),
Archana Patni7d40e962015-10-08 01:42:07 +0530108/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
109/* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),
robbie zhangc9d97292015-08-21 09:47:34 -0700110/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
111/* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP),
112/* UART0_RXD */ /* GPP_C8 */
113/* UART0_TXD */ /* GPP_C9 */
114/* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP),
115/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 1, 20K_PD, DEEP),
116/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
117/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
118/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
119/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
120/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
121/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
122/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
123/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
124/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
125/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
126/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
127/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
128/* ITCH_SPI_CS */ /* GPP_D0 */
129/* ITCH_SPI_CLK */ /* GPP_D1 */
130/* ITCH_SPI_MISO_1 */ /* GPP_D2 */
131/* ITCH_SPI_MISO_0 */ /* GPP_D3 */
132/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
133/* EN_PP3300_DX_EMMC */ PAD_CFG_GPO(GPP_D5, 1, DEEP),
134/* EN_PP1800_DX_EMMC */ PAD_CFG_GPO(GPP_D6, 1, DEEP),
135/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
136/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
137 PAD_CFG_GPO(GPP_D9, 0, DEEP),
138/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP),
139/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 1, DEEP),
140/* EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_D12, 1, DEEP),
141/* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),
142/* ISH_UART0_TXD */ /* GPP_D14 */
143/* ISH_UART0_RTS */ /* GPP_D15 */
144/* ISH_UART0_CTS */ /* GPP_D16 */
145/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
146/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
147/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
148/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
149/* ITCH_SPI_D2 */ /* GPP_D21 */
150/* ITCH_SPI_D3 */ /* GPP_D22 */
151/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
152/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP),
153/* SATAXPCIE1 */ /* GPP_E1 */
154/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
155/* CPU_GP0 */ /* GPP_E3 */
156/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
157/* SATA_DEVSLP1 */ /* GPP_E5 */
158/* SATA_DEVSLP2 */ /* GPP_E6 */
159/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP),
160/* SATALED# */ /* GPP_E8 */
161/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
162/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
163/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
164/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
165/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
166/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
167/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
168/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
169/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
170/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
171/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
172/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
173/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
174/* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP),
175/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
176/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
177/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
178/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
179/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
180/* I2C2_SDA */ /* GPP_F4 */
181/* I2C2_SCL */ /* GPP_F5 */
182/* I2C3_SDA */ /* GPP_F6 */
183/* I2C3_SCL */ /* GPP_F7 */
184/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
185/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
186/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
187/* I2C5_SCL */ /* GPP_F11 */
188/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
189/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
190/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
191/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
192/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
193/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
194/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
195/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
196/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
197/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
198/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
199 /* GPP_F23 */
200/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
201/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
202/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
203/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
204/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
205/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
206/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
207/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
208/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
209/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
210/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
211/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
212/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
213/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
214/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
215 /* GPD7 */
216/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
217/* PCH_SLP_WLAN# */ /* GPD9 */
218/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
219/* LANPHYC */ /* GPD11 */
Lee Leahyc4210412015-06-29 11:37:56 -0700220};
Wenkai Du1105fad2015-08-21 13:11:00 -0700221
222/* Early pad configuration in romstage. */
223static const struct pad_config early_gpio_table[] = {
224/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
225/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
226};
227
Lee Leahyc4210412015-06-29 11:37:56 -0700228#endif
Wenkai Du3b169252015-08-24 10:31:30 -0700229
230#endif