Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 2 | |
| 3 | #include <arch/cache.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <delay.h> |
| 8 | #include <edid.h> |
| 9 | #include <gpio.h> |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 10 | #include <string.h> |
| 11 | #include <soc/addressmap.h> |
| 12 | #include <soc/clock.h> |
| 13 | #include <soc/display.h> |
| 14 | #include <soc/edp.h> |
Yakir Yang | 68f42be | 2015-04-29 10:08:12 -0500 | [diff] [blame] | 15 | #include <soc/hdmi.h> |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 16 | #include <soc/gpio.h> |
| 17 | #include <soc/grf.h> |
| 18 | #include <soc/soc.h> |
| 19 | #include <soc/vop.h> |
Patrick Rudolph | 8b56c8c | 2020-02-19 12:57:00 +0100 | [diff] [blame] | 20 | #include <framebuffer_info.h> |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 21 | |
| 22 | #include "chip.h" |
| 23 | |
Elyes HAOUAS | f3ca88b | 2018-05-25 09:52:45 +0200 | [diff] [blame] | 24 | void rk_display_init(struct device *dev, u32 lcdbase, unsigned long fb_size) |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 25 | { |
| 26 | struct edid edid; |
Lin Huang | b9a7877 | 2016-04-25 18:50:55 +0800 | [diff] [blame] | 27 | uint32_t val; |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 28 | struct soc_rockchip_rk3288_config *conf = dev->chip_info; |
| 29 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
| 30 | uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 31 | enum vop_modes detected_mode = VOP_MODE_UNKNOWN; |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 32 | |
| 33 | printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); |
| 34 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
| 35 | dcache_clean_invalidate_by_mva((void *)lower, upper - lower); |
| 36 | mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); |
| 37 | |
Yakir Yang | 68f42be | 2015-04-29 10:08:12 -0500 | [diff] [blame] | 38 | switch (conf->vop_mode) { |
David Hendricks | cc82851 | 2015-06-25 18:00:37 -0700 | [diff] [blame] | 39 | case VOP_MODE_NONE: |
| 40 | return; |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 41 | case VOP_MODE_AUTO_DETECT: |
| 42 | /* try EDP first, then HDMI */ |
| 43 | case VOP_MODE_EDP: |
| 44 | printk(BIOS_DEBUG, "Attempting to setup EDP display.\n"); |
Yakir Yang | 68f42be | 2015-04-29 10:08:12 -0500 | [diff] [blame] | 45 | rkclk_configure_edp(); |
| 46 | rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); |
Lin Huang | b9a7877 | 2016-04-25 18:50:55 +0800 | [diff] [blame] | 47 | |
| 48 | /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */ |
| 49 | write32(&rk3288_grf->soc_con12, RK_SETBITS(1 << 4)); |
| 50 | |
| 51 | /* select epd signal from vop0 or vop1 */ |
| 52 | val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) : |
| 53 | RK_CLRBITS(1 << 5); |
| 54 | write32(&rk3288_grf->soc_con6, val); |
| 55 | |
| 56 | rk_edp_init(); |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 57 | |
| 58 | if (rk_edp_get_edid(&edid) == 0) { |
| 59 | detected_mode = VOP_MODE_EDP; |
| 60 | break; |
| 61 | } else { |
| 62 | printk(BIOS_WARNING, "Cannot get EDID from EDP.\n"); |
| 63 | if (conf->vop_mode == VOP_MODE_EDP) |
| 64 | return; |
Yakir Yang | 68f42be | 2015-04-29 10:08:12 -0500 | [diff] [blame] | 65 | } |
Arthur Heymans | 507b074 | 2022-03-24 01:16:34 +0100 | [diff] [blame] | 66 | __fallthrough; |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 67 | case VOP_MODE_HDMI: |
| 68 | printk(BIOS_DEBUG, "Attempting to setup HDMI display.\n"); |
| 69 | rkclk_configure_hdmi(); |
| 70 | rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz); |
| 71 | rk_hdmi_init(conf->vop_id); |
| 72 | |
| 73 | if (rk_hdmi_get_edid(&edid) == 0) { |
| 74 | detected_mode = VOP_MODE_HDMI; |
| 75 | break; |
| 76 | } else { |
| 77 | printk(BIOS_WARNING, "Cannot get EDID from HDMI.\n"); |
| 78 | if (conf->vop_mode == VOP_MODE_HDMI) |
| 79 | return; |
| 80 | } |
Arthur Heymans | 507b074 | 2022-03-24 01:16:34 +0100 | [diff] [blame] | 81 | __fallthrough; |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 82 | default: |
| 83 | printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n"); |
| 84 | return; |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 85 | } |
| 86 | |
David Hendricks | 7dbf9c6 | 2015-07-30 18:49:48 -0700 | [diff] [blame] | 87 | if (rkclk_configure_vop_dclk(conf->vop_id, edid.mode.pixel_clock * KHz)) { |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 88 | printk(BIOS_WARNING, "config vop err\n"); |
| 89 | return; |
| 90 | } |
| 91 | |
Julius Werner | 6911219 | 2016-03-14 17:29:55 -0700 | [diff] [blame] | 92 | edid_set_framebuffer_bits_per_pixel(&edid, |
Julius Werner | 2b6db97 | 2016-04-06 12:50:40 -0700 | [diff] [blame] | 93 | conf->framebuffer_bits_per_pixel, 0); |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 94 | rkvop_mode_set(conf->vop_id, &edid, detected_mode); |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 95 | |
Lin Huang | 152e675 | 2016-10-20 14:22:11 -0700 | [diff] [blame] | 96 | rkvop_prepare(conf->vop_id, &edid); |
| 97 | rkvop_enable(conf->vop_id, lcdbase); |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 98 | |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 99 | switch (detected_mode) { |
| 100 | case VOP_MODE_HDMI: |
Yakir Yang | 68f42be | 2015-04-29 10:08:12 -0500 | [diff] [blame] | 101 | if (rk_hdmi_enable(&edid)) { |
| 102 | printk(BIOS_WARNING, "hdmi enable err\n"); |
| 103 | return; |
| 104 | } |
| 105 | |
| 106 | /* |
| 107 | * HACK: if we do remove this delay, HDMI TV may not show |
| 108 | * anythings. So we make an delay here, ensure TV have |
| 109 | * enough time to respond. |
| 110 | */ |
| 111 | mdelay(2000); |
| 112 | break; |
| 113 | |
David Hendricks | af42f06 | 2015-06-17 13:47:28 -0700 | [diff] [blame] | 114 | case VOP_MODE_EDP: |
Yakir Yang | 68f42be | 2015-04-29 10:08:12 -0500 | [diff] [blame] | 115 | default: |
Lin Huang | a09b338 | 2016-10-23 14:17:25 -0700 | [diff] [blame] | 116 | if (rk_edp_prepare()) { |
| 117 | printk(BIOS_WARNING, "edp prepare err\n"); |
| 118 | return; |
| 119 | } |
Yakir Yang | 68f42be | 2015-04-29 10:08:12 -0500 | [diff] [blame] | 120 | if (rk_edp_enable()) { |
| 121 | printk(BIOS_WARNING, "edp enable err\n"); |
| 122 | return; |
| 123 | } |
| 124 | mainboard_power_on_backlight(); |
| 125 | break; |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 126 | } |
| 127 | |
Patrick Rudolph | 8b56c8c | 2020-02-19 12:57:00 +0100 | [diff] [blame] | 128 | fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)lcdbase); |
huang lin | 40f558e | 2014-09-19 14:51:52 +0800 | [diff] [blame] | 129 | } |