blob: 192580b534cdebfe245a961de4db383239178bb3 [file] [log] [blame]
huang lin40f558e2014-09-19 14:51:52 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010017 * Foundation, Inc.
huang lin40f558e2014-09-19 14:51:52 +080018 */
19
20#include <arch/cache.h>
21#include <arch/io.h>
22#include <console/console.h>
23#include <device/device.h>
24#include <delay.h>
25#include <edid.h>
26#include <gpio.h>
27#include <stdlib.h>
28#include <stddef.h>
29#include <string.h>
30#include <soc/addressmap.h>
31#include <soc/clock.h>
32#include <soc/display.h>
33#include <soc/edp.h>
Yakir Yang68f42be2015-04-29 10:08:12 -050034#include <soc/hdmi.h>
huang lin40f558e2014-09-19 14:51:52 +080035#include <soc/gpio.h>
36#include <soc/grf.h>
37#include <soc/soc.h>
38#include <soc/vop.h>
39
40#include "chip.h"
41
42void rk_display_init(device_t dev, u32 lcdbase,
43 unsigned long fb_size)
44{
45 struct edid edid;
46 struct soc_rockchip_rk3288_config *conf = dev->chip_info;
47 uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
48 uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
49
50 printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase));
51 memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
52 dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
53 mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
54
Yakir Yang68f42be2015-04-29 10:08:12 -050055 switch (conf->vop_mode) {
56 case HDMI_MODE:
57 rkclk_configure_hdmi();
58 rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz);
59 rk_hdmi_init(conf->vop_id);
60 if (rk_hdmi_get_edid(&edid)) {
61 printk(BIOS_WARNING, "can not get edid\n");
62 return;
63 }
64 break;
huang lin40f558e2014-09-19 14:51:52 +080065
Yakir Yang68f42be2015-04-29 10:08:12 -050066 case EDP_MODE:
67 default:
68 rkclk_configure_edp();
69 rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
70 rk_edp_init(conf->vop_id);
71 if (rk_edp_get_edid(&edid)) {
72 printk(BIOS_WARNING, "can not get edid\n");
73 return;
74 }
75 break;
huang lin40f558e2014-09-19 14:51:52 +080076 }
77
78 if (rkclk_configure_vop_dclk(conf->vop_id, edid.pixel_clock * KHz)) {
79 printk(BIOS_WARNING, "config vop err\n");
80 return;
81 }
82
83 edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel;
84 edid.bytes_per_line = edid.ha * conf->framebuffer_bits_per_pixel / 8;
85 edid.x_resolution = edid.ha;
86 edid.y_resolution = edid.va;
Yakir Yang68f42be2015-04-29 10:08:12 -050087 rkvop_mode_set(conf->vop_id, &edid, conf->vop_mode);
huang lin40f558e2014-09-19 14:51:52 +080088
89 rkvop_enable(conf->vop_id, lcdbase, &edid);
90
Yakir Yang68f42be2015-04-29 10:08:12 -050091 switch (conf->vop_mode) {
92 case HDMI_MODE:
93 if (rk_hdmi_enable(&edid)) {
94 printk(BIOS_WARNING, "hdmi enable err\n");
95 return;
96 }
97
98 /*
99 * HACK: if we do remove this delay, HDMI TV may not show
100 * anythings. So we make an delay here, ensure TV have
101 * enough time to respond.
102 */
103 mdelay(2000);
104 break;
105
106 case EDP_MODE:
107 default:
108 if (rk_edp_enable()) {
109 printk(BIOS_WARNING, "edp enable err\n");
110 return;
111 }
112 mainboard_power_on_backlight();
113 break;
huang lin40f558e2014-09-19 14:51:52 +0800114 }
115
116 set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase);
huang lin40f558e2014-09-19 14:51:52 +0800117}