blob: 96f7d782c6526d7f8c8a9bfbf46534287996e486 [file] [log] [blame]
Sean Rhodesab5b7b32021-10-22 14:33:27 +01001chip soc/intel/skylake
2# CPU
3 # Enable Enhanced Intel SpeedStep
4 register "eist_enable" = "1"
5
6 # Graphics
7 # IGD Displays
8 register "panel_cfg" = "{
9 .up_delay_ms = 0, // T3
10 .backlight_on_delay_ms = 0, // T7
11 .backlight_off_delay_ms = 0, // T9
12 .down_delay_ms = 0, // T10
13 .cycle_delay_ms = 500, // T12
14 .backlight_pwm_hz = 200, // PWM
15 }"
16
17 # FSP Memory
18 register "SaGv" = "SaGv_Enabled"
19
20# FSP Silicon
21 # Serial I/O
22 register "SerialIoDevMode" = "{
23 [PchSerialIoIndexI2C0] = PchSerialIoPci,
24 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
25 }"
26
27 # Power
28 register "PmConfigSlpS3MinAssert" = "2" # 50ms
29 register "PmConfigSlpS4MinAssert" = "3" # 1s
30 register "PmConfigSlpSusMinAssert" = "3" # 500ms
31 register "PmConfigSlpAMinAssert" = "3" # 2s
32
Sean Rhodesab5b7b32021-10-22 14:33:27 +010033 # PM Util
34 # GPE configuration
35 # Note that GPE events called out in ASL code rely on this
36 # route. i.e. If this route changes then the affected GPE
37 # offset bits also need to be changed.
38 # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
39 register "gpe0_dw0" = "GPP_B"
40 register "gpe0_dw1" = "GPP_C"
41 register "gpe0_dw2" = "GPP_E"
42
43 # Enable the correct decode ranges on the LPC bus.
44 register "lpc_ioe" = "LPC_IOE_EC_4E_4F |
45 LPC_IOE_KBC_60_64 |
46 LPC_IOE_EC_62_66"
47
48# Actual device tree.
Arthur Heymans69cd7292022-11-07 13:52:11 +010049 device cpu_cluster 0 on end
Sean Rhodesab5b7b32021-10-22 14:33:27 +010050
51 device domain 0 on
Sean Rhodes148f0752022-09-07 16:39:44 +010052 device ref igpu on end
53 device ref sa_thermal on end
54 device ref south_xhci on
Sean Rhodesab5b7b32021-10-22 14:33:27 +010055 # Motherboard USB Type C
56 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
Sean Rhodes220a47d2022-05-30 10:39:00 +010057 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
58
Sean Rhodesab5b7b32021-10-22 14:33:27 +010059 # Motherboard USB 3.0
60 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodes220a47d2022-05-30 10:39:00 +010061 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
62
Sean Rhodesab5b7b32021-10-22 14:33:27 +010063 # Daughterboard USB 3.0
64 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodes220a47d2022-05-30 10:39:00 +010065 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
66
Sean Rhodese36205d2022-08-30 10:10:57 +010067 # Internal Bluetooth
68 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
69
Sean Rhodesab5b7b32021-10-22 14:33:27 +010070 # Daughterboard SD Card
71 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
72
Sean Rhodes2eb2dce2022-05-26 20:56:14 +010073 # Webcam
74 register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodesab5b7b32021-10-22 14:33:27 +010075 end
Sean Rhodes148f0752022-09-07 16:39:44 +010076 device ref thermal on end
77 device ref i2c0 on
Sean Rhodesab5b7b32021-10-22 14:33:27 +010078 chip drivers/i2c/hid
79 register "generic.hid" = ""STAR0001""
80 register "generic.desc" = ""Touchpad""
81 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
Matt DeVillier2cf52d82022-09-01 15:09:24 -050082 register "generic.detect" = "1"
Sean Rhodesab5b7b32021-10-22 14:33:27 +010083 register "hid_desc_reg_offset" = "0x20"
84 device i2c 2c on end
85 end
86 end
Sean Rhodes148f0752022-09-07 16:39:44 +010087 device ref heci1 on end
88 device ref sata on
Sean Rhodesab5b7b32021-10-22 14:33:27 +010089 register "SataSalpSupport" = "1"
90 # Port 1
91 register "SataPortsEnable[1]" = "1"
92 register "SataPortsDevSlp[1]" = "1"
93 end
Sean Rhodes148f0752022-09-07 16:39:44 +010094 device ref uart2 on end
95 device ref pcie_rp6 on
Sean Rhodesab5b7b32021-10-22 14:33:27 +010096 register "PcieRpEnable[5]" = "1"
97 register "PcieRpClkReqSupport[5]" = "1"
98 register "PcieRpClkReqNumber[5]" = "4"
99 register "PcieRpClkSrcNumber[5]" = "4"
100 register "PcieRpLtrEnable[5]" = "1"
101 chip drivers/wifi/generic
102 device generic 0 on end
103 end
104 end
Sean Rhodes148f0752022-09-07 16:39:44 +0100105 device ref pcie_rp9 on
Sean Rhodesab5b7b32021-10-22 14:33:27 +0100106 register "PcieRpEnable[8]" = "1"
107 register "PcieRpClkReqSupport[8]" = "1"
108 register "PcieRpClkReqNumber[8]" = "0"
109 register "PcieRpClkSrcNumber[8]" = "0"
110 register "PcieRpLtrEnable[8]" = "1"
111 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
112 end
Sean Rhodes148f0752022-09-07 16:39:44 +0100113 device ref uart0 on end
Felix Singeraffd4562023-11-12 17:06:28 +0000114 device ref lpc_espi on
Sean Rhodesab5b7b32021-10-22 14:33:27 +0100115 register "gen1_dec" = "0x000c0681"
116 register "gen2_dec" = "0x000c1641"
117 register "gen3_dec" = "0x00000069"
118 register "gen4_dec" = "0x0000006d"
119
120 chip ec/starlabs/merlin
121 # Port pair 4Eh/4Fh
122 device pnp 4e.00 on end # IO Interface
123 device pnp 4e.01 off end # Com 1
124 device pnp 4e.02 off end # Com 2
125 device pnp 4e.04 off end # System Wake-Up
126 device pnp 4e.05 off end # PS/2 Mouse
127 device pnp 4e.06 on # PS/2 Keyboard
128 io 0x60 = 0x0060
129 io 0x62 = 0x0064
130 irq 0x70 = 1
131 end
132 device pnp 4e.0a off end # Consumer IR
133 device pnp 4e.0f off end # Shared Memory/Flash Interface
134 device pnp 4e.10 off end # RTC-like Timer
135 device pnp 4e.11 off end # Power Management Channel 1
136 device pnp 4e.12 off end # Power Management Channel 2
137 device pnp 4e.13 off end # Serial Peripheral Interface
138 device pnp 4e.14 off end # Platform EC Interface
139 device pnp 4e.17 off end # Power Management Channel 3
140 device pnp 4e.18 off end # Power Management Channel 4
141 device pnp 4e.19 off end # Power Management Channel 5
142 end
143 end
Sean Rhodes148f0752022-09-07 16:39:44 +0100144 device ref hda on end
145 device ref smbus on end
146 device ref fast_spi on end
Sean Rhodesab5b7b32021-10-22 14:33:27 +0100147 end
148end