Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Ivy Jian | 49df72a | 2021-04-08 13:37:47 +0800 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 4 | #include <baseboard/gpio.h> |
| 5 | #include <baseboard/variants.h> |
| 6 | #include <commonlib/helpers.h> |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 7 | #include <delay.h> |
| 8 | #include <gpio.h> |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 9 | #include <soc/gpio.h> |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 10 | |
| 11 | /* GPIO configuration in ramstage*/ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 12 | /* Please make sure that *ALL* GPIOs are configured in this table */ |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 13 | static const struct soc_amd_gpio base_gpio_table[] = { |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 14 | /* PWR_BTN_L */ |
| 15 | PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), |
| 16 | /* SYS_RESET_L */ |
| 17 | PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), |
| 18 | /* WAKE_L */ |
Felix Held | f8e440c | 2021-03-24 00:17:35 +0100 | [diff] [blame] | 19 | PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 20 | /* EN_PWR_FP */ |
| 21 | PAD_GPO(GPIO_3, HIGH), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 22 | /* SOC_PEN_DETECT_ODL */ |
| 23 | PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), |
Karthikeyan Ramasubramanian | 750abb1 | 2021-10-25 22:50:33 -0600 | [diff] [blame] | 24 | /* SD_AUX_RESET_L */ |
| 25 | PAD_GPO(GPIO_5, HIGH), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 26 | /* EN_PP3300_WLAN */ |
Martin Roth | 3db4992 | 2021-04-05 17:35:59 -0600 | [diff] [blame] | 27 | PAD_GPO(GPIO_6, HIGH), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 28 | /* EN_PP3300_TCHPAD */ |
Karthikeyan Ramasubramanian | 0f41912 | 2021-03-30 15:34:47 -0600 | [diff] [blame] | 29 | PAD_GPO(GPIO_7, HIGH), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 30 | /* EN_PWR_WWAN_X */ |
Martin Roth | 3db4992 | 2021-04-05 17:35:59 -0600 | [diff] [blame] | 31 | PAD_GPO(GPIO_8, HIGH), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 32 | /* SOC_TCHPAD_INT_ODL */ |
Raul E Rangel | 3cb69c2 | 2021-04-30 09:58:18 -0600 | [diff] [blame] | 33 | PAD_SCI(GPIO_9, PULL_NONE, EDGE_HIGH), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 34 | /* S0A3 */ |
| 35 | PAD_NF(GPIO_10, S0A3, PULL_NONE), |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 36 | /* SOC_FP_RST_L - Brought high in finalize */ |
| 37 | PAD_GPO(GPIO_11, LOW), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 38 | /* SLP_S3_GATED */ |
| 39 | PAD_GPO(GPIO_12, LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 40 | /* GPIO_13 - GPIO_15: Not available */ |
| 41 | /* USB_OC0_L */ |
| 42 | PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 43 | /* SOC_SAR_INT_L */ |
Raul E Rangel | 3cb69c2 | 2021-04-30 09:58:18 -0600 | [diff] [blame] | 44 | PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 45 | /* WWAN_AUX_RESET_L */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 46 | PAD_GPO(GPIO_18, HIGH), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 47 | /* I2C3_SCL */ |
| 48 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 49 | /* I2C3_SDA */ |
| 50 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 51 | /* SOC_FP_INT_L */ |
Raul E Rangel | 3cb69c2 | 2021-04-30 09:58:18 -0600 | [diff] [blame] | 52 | PAD_SCI(GPIO_21, PULL_NONE, EDGE_LOW), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 53 | /* EC_SOC_WAKE_ODL */ |
Raul E Rangel | 3cb69c2 | 2021-04-30 09:58:18 -0600 | [diff] [blame] | 54 | PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 55 | /* AC_PRES */ |
| 56 | PAD_NF(GPIO_23, AC_PRES, PULL_UP), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 57 | /* WWAN_RST_L */ |
Martin Roth | 3db4992 | 2021-04-05 17:35:59 -0600 | [diff] [blame] | 58 | PAD_GPO(GPIO_24, HIGH), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 59 | /* GPIO_25: Not available */ |
| 60 | /* PCIE_RST0_L */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 61 | PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 62 | /* PCIE_RST1_L */ |
Martin Roth | 8baa9df | 2021-07-20 16:49:34 -0600 | [diff] [blame] | 63 | PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 64 | /* GPIO_28: Not available */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 65 | /* WLAN_AUX_RESET (Active HIGH)*/ |
Martin Roth | 3db4992 | 2021-04-05 17:35:59 -0600 | [diff] [blame] | 66 | PAD_GPO(GPIO_29, LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 67 | /* ESPI_CS_L */ |
| 68 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
Karthikeyan Ramasubramanian | fcb9716 | 2021-06-01 23:45:34 -0600 | [diff] [blame] | 69 | /* EN_SPKR */ |
| 70 | PAD_GPO(GPIO_31, HIGH), |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 71 | /* Unused */ |
| 72 | PAD_NC(GPIO_32), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 73 | /* GPIO_33 - GPIO_39: Not available */ |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 74 | /* SSD_AUX_RESET_L */ |
Martin Roth | 3db4992 | 2021-04-05 17:35:59 -0600 | [diff] [blame] | 75 | PAD_GPO(GPIO_40, HIGH), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 76 | /* GPIO_41: Not available */ |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 77 | /* WWAN_DPR_SAR_ODL */ |
| 78 | PAD_GPO(GPIO_42, LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 79 | /* GPIO_43 - GPIO_66: Not available */ |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 80 | /* SOC_BIOS_WP_L */ |
| 81 | PAD_GPI(GPIO_67, PULL_NONE), |
| 82 | /* EN_PP3300_TCHSCR */ |
Martin Roth | 8baa9df | 2021-07-20 16:49:34 -0600 | [diff] [blame] | 83 | PAD_GPO(GPIO_68, HIGH), |
Karthikeyan Ramasubramanian | 750abb1 | 2021-10-25 22:50:33 -0600 | [diff] [blame] | 84 | /* Unused */ |
| 85 | PAD_NC(GPIO_69), |
Karthikeyan Ramasubramanian | fcb9716 | 2021-06-01 23:45:34 -0600 | [diff] [blame] | 86 | /* Unused TP27 */ |
| 87 | PAD_NC(GPIO_70), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 88 | /* GPIO_71 - GPIO_73: Not available */ |
Karthikeyan Ramasubramanian | fcb9716 | 2021-06-01 23:45:34 -0600 | [diff] [blame] | 89 | /* Unused TP49 */ |
| 90 | PAD_NC(GPIO_74), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 91 | /* RAM_ID_2 / DEV_BEEP_LRCLK */ |
| 92 | PAD_GPI(GPIO_75, PULL_NONE), |
| 93 | /* EN_PP3300_CAM */ |
Ivy Jian | 7a347af | 2021-04-01 17:22:48 +0800 | [diff] [blame] | 94 | PAD_GPO(GPIO_76, HIGH), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 95 | /* GPIO_77 - GPIO_83: Not available */ |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 96 | /* EC_SOC_INT_ODL */ |
| 97 | PAD_GPI(GPIO_84, PULL_NONE), |
Karthikeyan Ramasubramanian | b418298 | 2021-10-26 16:55:35 -0600 | [diff] [blame] | 98 | /* GSC_SOC_INT_L */ |
| 99 | PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
Martin Roth | 6324198 | 2021-03-21 18:45:16 -0600 | [diff] [blame] | 100 | /* ESPI_SOC_CLK */ |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 101 | PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 102 | /* RAM_ID_1 / DEV_BEEP_DATA */ |
| 103 | PAD_GPI(GPIO_87, PULL_NONE), |
| 104 | /* RAM_ID_3 / DEV_BEEP_BCLK */ |
| 105 | PAD_GPI(GPIO_88, PULL_NONE), |
| 106 | /* TCHSCR_INT_ODL */ |
| 107 | PAD_GPI(GPIO_89, PULL_NONE), |
| 108 | /* HP_INT_ODL */ |
| 109 | PAD_GPI(GPIO_90, PULL_NONE), |
Karthikeyan Ramasubramanian | 1b7dac1 | 2021-07-21 14:54:16 -0600 | [diff] [blame] | 110 | /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 111 | PAD_GPI(GPIO_91, PULL_NONE), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 112 | /* CLK_REQ0_L */ |
| 113 | PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), |
| 114 | /* GPIO_93 - GPIO_103: Not available */ |
Mathew King | 447a681 | 2021-03-16 13:04:26 -0600 | [diff] [blame] | 115 | /* ESPI1_DATA0 */ |
| 116 | PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), |
| 117 | /* ESPI1_DATA1 */ |
| 118 | PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), |
| 119 | /* ESPI1_DATA2 */ |
Felix Held | 26806ae | 2021-11-03 03:29:21 +0100 | [diff] [blame^] | 120 | PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE), |
Mathew King | 447a681 | 2021-03-16 13:04:26 -0600 | [diff] [blame] | 121 | /* ESPI1_DATA3 */ |
| 122 | PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), |
Martin Roth | 6324198 | 2021-03-21 18:45:16 -0600 | [diff] [blame] | 123 | /* ESPI_ALERT_L */ |
| 124 | PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 125 | /* RAM_ID_0 / DEV_BEEP_EN */ |
| 126 | PAD_GPI(GPIO_109, PULL_NONE), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 127 | /* GPIO_110 - GPIO_112: Not available */ |
| 128 | /* I2C2_SCL */ |
| 129 | PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), |
| 130 | /* I2C2_SDA */ |
| 131 | PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), |
| 132 | /* CLK_REQ1_L */ |
| 133 | PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), |
| 134 | /* CLK_REQ2_L */ |
| 135 | PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), |
| 136 | /* GPIO_117 - GPIO_119: Not available */ |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 137 | /* TCHSCR_REPORT_EN */ |
| 138 | PAD_GPO(GPIO_120, LOW), |
| 139 | /* TCHSCR_RESET_L */ |
| 140 | PAD_GPO(GPIO_121, LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 141 | /* GPIO_122 - GPIO_128: Not available */ |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 142 | /* SOC_DISABLE_DISP_BL */ |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 143 | PAD_GPO(GPIO_129, HIGH), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 144 | /* WLAN_DISABLE */ |
Martin Roth | 3db4992 | 2021-04-05 17:35:59 -0600 | [diff] [blame] | 145 | PAD_GPO(GPIO_130, LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 146 | /* CLK_REQ3_L */ |
| 147 | PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 148 | /* BT_DISABLE */ |
Karthikeyan Ramasubramanian | d84ce40 | 2021-03-30 16:27:59 -0600 | [diff] [blame] | 149 | PAD_GPO(GPIO_132, LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 150 | /* UART1_TXD */ |
| 151 | PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), |
| 152 | /* UART0_RXD */ |
| 153 | PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), |
| 154 | /* UART1_RXD */ |
| 155 | PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), |
| 156 | /* UART0_TXD */ |
| 157 | PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), |
Mathew King | 91a2cd4 | 2021-02-09 14:28:50 -0700 | [diff] [blame] | 158 | /* SOC_FPMCU_BOOT0 */ |
| 159 | PAD_GPO(GPIO_144, LOW), |
Mathew King | 6109c2c | 2021-01-28 14:55:12 -0700 | [diff] [blame] | 160 | /* I2C0_SCL */ |
| 161 | PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), |
| 162 | /* I2C0_SDA */ |
| 163 | PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), |
| 164 | /* I2C1_SCL */ |
| 165 | PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), |
| 166 | /* I2C1_SDA */ |
| 167 | PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 168 | }; |
| 169 | |
Mathew King | d490afb | 2021-03-11 08:25:52 -0700 | [diff] [blame] | 170 | /* Early GPIO configuration */ |
| 171 | static const struct soc_amd_gpio early_gpio_table[] = { |
Martin Roth | 8baa9df | 2021-07-20 16:49:34 -0600 | [diff] [blame] | 172 | /* Assert all AUX reset lines */ |
Karthikeyan Ramasubramanian | 750abb1 | 2021-10-25 22:50:33 -0600 | [diff] [blame] | 173 | /* SD_AUX_RESET_L */ |
| 174 | PAD_GPO(GPIO_5, LOW), |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 175 | /* WWAN_AUX_RESET_L */ |
| 176 | PAD_GPO(GPIO_18, LOW), |
| 177 | /* WLAN_AUX_RESET (ACTIVE HIGH) */ |
| 178 | PAD_GPO(GPIO_29, HIGH), |
| 179 | /* SSD_AUX_RESET_L */ |
| 180 | PAD_GPO(GPIO_40, LOW), |
Karthikeyan Ramasubramanian | 750abb1 | 2021-10-25 22:50:33 -0600 | [diff] [blame] | 181 | /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ |
| 182 | PAD_NC(GPIO_69), |
| 183 | /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 184 | PAD_NC(GPIO_70), |
Martin Roth | 8baa9df | 2021-07-20 16:49:34 -0600 | [diff] [blame] | 185 | |
| 186 | /* Deassert PCIe Reset lines */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 187 | /* PCIE_RST0_L */ |
| 188 | PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), |
Martin Roth | 8baa9df | 2021-07-20 16:49:34 -0600 | [diff] [blame] | 189 | /* PCIE_RST1_L */ |
| 190 | PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 191 | |
| 192 | /* Power on WLAN & WWAN */ |
Martin Roth | 3db4992 | 2021-04-05 17:35:59 -0600 | [diff] [blame] | 193 | /* EN_PP3300_WLAN */ |
| 194 | PAD_GPO(GPIO_6, HIGH), |
| 195 | /* EN_PWR_WWAN_X */ |
| 196 | PAD_GPO(GPIO_8, HIGH), |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 197 | |
Martin Roth | 049e994 | 2021-08-31 17:28:03 -0600 | [diff] [blame] | 198 | /* Put WWAN into reset */ |
| 199 | /* WWAN_RST_L */ |
| 200 | PAD_GPO(GPIO_24, LOW), |
Martin Roth | 049e994 | 2021-08-31 17:28:03 -0600 | [diff] [blame] | 201 | |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 202 | /* Enable ESPI, GSC Interrupt & I2C Communication */ |
Karthikeyan Ramasubramanian | b418298 | 2021-10-26 16:55:35 -0600 | [diff] [blame] | 203 | /* Unused */ |
| 204 | PAD_NC(GPIO_3), |
Karthikeyan Ramasubramanian | 8f7fca5 | 2021-03-15 10:31:37 -0600 | [diff] [blame] | 205 | /* I2C3_SCL */ |
| 206 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 207 | /* I2C3_SDA */ |
| 208 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
Martin Roth | 6324198 | 2021-03-21 18:45:16 -0600 | [diff] [blame] | 209 | /* ESPI_CS_L */ |
| 210 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
Karthikeyan Ramasubramanian | b418298 | 2021-10-26 16:55:35 -0600 | [diff] [blame] | 211 | /* GSC_SOC_INT_L */ |
| 212 | PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
Martin Roth | 6324198 | 2021-03-21 18:45:16 -0600 | [diff] [blame] | 213 | /* ESPI_SOC_CLK */ |
| 214 | PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), |
Mathew King | d5baf6d | 2021-03-05 08:56:59 -0700 | [diff] [blame] | 215 | /* ESPI1_DATA0 */ |
| 216 | PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), |
| 217 | /* ESPI1_DATA1 */ |
| 218 | PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), |
| 219 | /* ESPI1_DATA2 */ |
Felix Held | 26806ae | 2021-11-03 03:29:21 +0100 | [diff] [blame^] | 220 | PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE), |
Mathew King | d5baf6d | 2021-03-05 08:56:59 -0700 | [diff] [blame] | 221 | /* ESPI1_DATA3 */ |
| 222 | PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), |
| 223 | /* ESPI_ALERT_L */ |
| 224 | PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 225 | |
| 226 | /* Enable UART 0 */ |
Mathew King | cec5245 | 2021-03-16 12:49:26 -0600 | [diff] [blame] | 227 | /* UART0_RXD */ |
| 228 | PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), |
| 229 | /* UART0_TXD */ |
| 230 | PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), |
Hsuan Ting Chen | 3bfe46c | 2021-10-08 15:31:00 +0800 | [diff] [blame] | 231 | |
| 232 | /* Support EC trusted */ |
| 233 | /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ |
| 234 | PAD_GPI(GPIO_91, PULL_NONE), |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 235 | }; |
| 236 | |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 237 | /* Power-on timing requirements: |
| 238 | * Fibocom 350-GL: |
| 239 | * FCP0# goes high (GPIO 6) to Reset# high (GPIO 24): 20ms min |
| 240 | * FCP0# goes high (GPIO 6) to PERST# high (GPIO 26): 100ms min |
| 241 | * PERST# high (GPIO 26) to PCIE Training (FSP-M): 23ms min |
| 242 | * |
| 243 | * Realtek RTL8852AE: |
| 244 | * Power (3.3 V) valid to PERST# high (GPIO_26): 50ms min |
| 245 | * |
| 246 | * Qualcomm WCN6856: |
| 247 | * Power (3.3 V) valid to PERST# high (GPIO_26): 50ms min |
| 248 | * |
| 249 | * RTS5250S / RTS5227S / RTS5261S |
| 250 | * Power (3.3 V) valid to PERST# high (GPIO_69/70): 1ms min |
| 251 | * |
| 252 | * PCIe spec: |
| 253 | * Power (3.3 V) valid to PERST# high (GPIO_26): 50ms min (SUGGESTED) |
| 254 | * |
| 255 | * NVME adapters planned for Guybrush: |
| 256 | * No power on timings specified - Assumed to require PCIe Spec suggested |
| 257 | * guidelines. Testing seems to bear out this assumption. |
| 258 | */ |
| 259 | |
| 260 | static const struct soc_amd_gpio bootblock_gpio_table[] = { |
Martin Roth | 049e994 | 2021-08-31 17:28:03 -0600 | [diff] [blame] | 261 | /* Enable WWAN, Deassert WWAN reset, keep WWAN PCIe Aux reset asserted */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 262 | /* WWAN_RST_L */ |
| 263 | PAD_GPO(GPIO_24, HIGH), |
Martin Roth | 049e994 | 2021-08-31 17:28:03 -0600 | [diff] [blame] | 264 | |
| 265 | /* Enable WLAN */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 266 | /* WLAN_DISABLE */ |
| 267 | PAD_GPO(GPIO_130, LOW), |
| 268 | }; |
| 269 | |
Mathew King | ee10ce6 | 2021-03-04 15:34:37 -0700 | [diff] [blame] | 270 | /* GPIO configuration for sleep */ |
| 271 | static const struct soc_amd_gpio sleep_gpio_table[] = { |
| 272 | /* TODO: Fill sleep gpio configuration */ |
| 273 | }; |
| 274 | |
Martin Roth | 3360862 | 2021-05-20 20:41:18 -0600 | [diff] [blame] | 275 | /* PCIE_RST needs to be brought high before FSP-M runs */ |
| 276 | static const struct soc_amd_gpio pcie_gpio_table[] = { |
Martin Roth | 8baa9df | 2021-07-20 16:49:34 -0600 | [diff] [blame] | 277 | /* Deassert all AUX_RESET lines & PCIE_RST */ |
Karthikeyan Ramasubramanian | 750abb1 | 2021-10-25 22:50:33 -0600 | [diff] [blame] | 278 | /* SD_AUX_RESET_L */ |
| 279 | PAD_GPO(GPIO_5, HIGH), |
Martin Roth | 3360862 | 2021-05-20 20:41:18 -0600 | [diff] [blame] | 280 | /* WWAN_AUX_RESET_L */ |
| 281 | PAD_GPO(GPIO_18, HIGH), |
| 282 | /* WLAN_AUX_RESET (ACTIVE HIGH) */ |
| 283 | PAD_GPO(GPIO_29, LOW), |
| 284 | /* SSD_AUX_RESET_L */ |
| 285 | PAD_GPO(GPIO_40, HIGH), |
Karthikeyan Ramasubramanian | 750abb1 | 2021-10-25 22:50:33 -0600 | [diff] [blame] | 286 | /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ |
| 287 | PAD_NC(GPIO_69), |
| 288 | /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ |
Martin Roth | 3360862 | 2021-05-20 20:41:18 -0600 | [diff] [blame] | 289 | PAD_NC(GPIO_70), |
| 290 | /* PCIE_RST0_L */ |
| 291 | PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), |
| 292 | }; |
| 293 | |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 294 | static const struct soc_amd_gpio fpmcu_shutdown_gpio_table[] = { |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 295 | /* FPMCU_RST_L */ |
| 296 | PAD_GPO(GPIO_11, LOW), |
| 297 | /* EN_PWR_FP */ |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 298 | PAD_GPO(GPIO_3, LOW), |
| 299 | }; |
| 300 | |
| 301 | static const struct soc_amd_gpio fpmcu_disable_gpio_table[] = { |
| 302 | /* FPMCU_RST_L */ |
| 303 | PAD_NC(GPIO_11), |
| 304 | /* EN_PWR_FP */ |
| 305 | PAD_NC(GPIO_3), |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 306 | }; |
| 307 | |
Martin Roth | 3360862 | 2021-05-20 20:41:18 -0600 | [diff] [blame] | 308 | const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size) |
| 309 | { |
| 310 | *size = ARRAY_SIZE(pcie_gpio_table); |
| 311 | return pcie_gpio_table; |
| 312 | } |
| 313 | |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 314 | const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size) |
| 315 | { |
| 316 | *size = ARRAY_SIZE(bootblock_gpio_table); |
| 317 | return bootblock_gpio_table; |
| 318 | } |
| 319 | |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 320 | const struct soc_amd_gpio *__weak variant_base_gpio_table(size_t *size) |
| 321 | { |
| 322 | *size = ARRAY_SIZE(base_gpio_table); |
| 323 | return base_gpio_table; |
| 324 | } |
| 325 | const struct soc_amd_gpio *__weak variant_override_gpio_table(size_t *size) |
| 326 | { |
| 327 | *size = 0; |
| 328 | return NULL; |
| 329 | } |
| 330 | |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 331 | const struct soc_amd_gpio * __weak variant_early_override_gpio_table(size_t *size) |
| 332 | { |
Martin Roth | 049e994 | 2021-08-31 17:28:03 -0600 | [diff] [blame] | 333 | /* Note that when overriding this, board ID & CBI is not available */ |
Martin Roth | 324cea9 | 2021-05-03 16:21:11 -0600 | [diff] [blame] | 334 | *size = 0; |
| 335 | return NULL; |
| 336 | } |
| 337 | |
| 338 | const struct soc_amd_gpio * __weak variant_bootblock_override_gpio_table(size_t *size) |
| 339 | { |
| 340 | *size = 0; |
| 341 | return NULL; |
| 342 | } |
| 343 | |
Martin Roth | 3360862 | 2021-05-20 20:41:18 -0600 | [diff] [blame] | 344 | const struct soc_amd_gpio * __weak variant_pcie_override_gpio_table(size_t *size) |
| 345 | { |
| 346 | *size = 0; |
| 347 | return NULL; |
| 348 | } |
| 349 | |
Mathew King | d490afb | 2021-03-11 08:25:52 -0700 | [diff] [blame] | 350 | const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size) |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 351 | { |
Mathew King | d490afb | 2021-03-11 08:25:52 -0700 | [diff] [blame] | 352 | *size = ARRAY_SIZE(early_gpio_table); |
| 353 | return early_gpio_table; |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 354 | } |
Mathew King | ee10ce6 | 2021-03-04 15:34:37 -0700 | [diff] [blame] | 355 | |
| 356 | const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size) |
| 357 | { |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 358 | if (acpi_get_sleep_type() == ACPI_S5) |
| 359 | return variant_fpmcu_shutdown_gpio_table(size); |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 360 | |
Mathew King | ee10ce6 | 2021-03-04 15:34:37 -0700 | [diff] [blame] | 361 | *size = ARRAY_SIZE(sleep_gpio_table); |
| 362 | return sleep_gpio_table; |
| 363 | } |
Ivy Jian | 49df72a | 2021-04-08 13:37:47 +0800 | [diff] [blame] | 364 | |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 365 | const __weak struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) |
| 366 | { |
| 367 | *size = ARRAY_SIZE(fpmcu_shutdown_gpio_table); |
| 368 | return fpmcu_shutdown_gpio_table; |
| 369 | } |
| 370 | |
| 371 | const __weak struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) |
| 372 | { |
| 373 | *size = ARRAY_SIZE(fpmcu_disable_gpio_table); |
| 374 | return fpmcu_disable_gpio_table; |
| 375 | } |
| 376 | |
Ivy Jian | 49df72a | 2021-04-08 13:37:47 +0800 | [diff] [blame] | 377 | __weak void variant_fpmcu_reset(void) |
| 378 | { |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 379 | size_t size; |
| 380 | const struct soc_amd_gpio *gpio_table; |
| 381 | |
Ivy Jian | 49df72a | 2021-04-08 13:37:47 +0800 | [diff] [blame] | 382 | if (acpi_get_sleep_type() == ACPI_S3) |
| 383 | return; |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 384 | /* If the system is not resuming from S3, power off the FPMCU */ |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 385 | gpio_table = variant_fpmcu_shutdown_gpio_table(&size); |
| 386 | gpio_configure_pads(gpio_table, size); |
Ivy Jian | 49df72a | 2021-04-08 13:37:47 +0800 | [diff] [blame] | 387 | } |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 388 | |
| 389 | __weak void variant_finalize_gpios(void) |
| 390 | { |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 391 | size_t size; |
| 392 | const struct soc_amd_gpio *gpio_table; |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 393 | |
| 394 | if (variant_has_fpmcu()) { |
| 395 | if (acpi_get_sleep_type() == ACPI_S3) |
| 396 | return; |
| 397 | /* Deassert the FPMCU reset to enable the FPMCU */ |
| 398 | gpio_set(GPIO_11, 1); /* FPMCU_RST_L */ |
| 399 | } else { |
Rob Barnes | 9a56ff9 | 2021-10-27 11:25:43 -0600 | [diff] [blame] | 400 | gpio_table = variant_fpmcu_disable_gpio_table(&size); |
| 401 | gpio_configure_pads(gpio_table, size); |
Martin Roth | 266dfc9 | 2021-07-21 13:31:48 -0600 | [diff] [blame] | 402 | } |
| 403 | } |