Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 secunet Security Networks AG |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | |
| 20 | #include <arch/io.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 21 | #include <device/pci_def.h> |
| 22 | #include <arch/acpi.h> |
| 23 | |
| 24 | #include "gm45.h" |
| 25 | |
| 26 | void init_iommu() |
| 27 | { |
| 28 | /* FIXME: proper test? */ |
| 29 | int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; |
| 30 | int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); |
| 31 | |
| 32 | MCHBAR32(0x28) = IOMMU_BASE1 | 1; /* HDA @ 0:1b.0 */ |
| 33 | if (stepping != STEPPING_B2) { |
| 34 | /* The official workaround is to run SMM every 64ms. |
| 35 | The only winning move is not to play. */ |
| 36 | MCHBAR32(0x18) = IOMMU_BASE2 | 1; /* IGD @ 0:2.0-1 */ |
| 37 | } else { |
| 38 | /* write-once, so lock it down */ |
| 39 | MCHBAR32(0x18) = 0; /* disable IOMMU for IGD @ 0:2.0-1 */ |
| 40 | } |
| 41 | if (me_active) { |
| 42 | MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ |
Damien Zammit | 88af372 | 2016-08-27 00:35:48 +1000 | [diff] [blame] | 43 | } else { |
| 44 | MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 45 | } |
| 46 | MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ |
| 47 | |
| 48 | /* clear GTT */ |
| 49 | u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); |
| 50 | if (gtt & 0x400) { /* VT mode */ |
Furquan Shaikh | 25f75b2 | 2016-08-29 22:51:41 -0700 | [diff] [blame^] | 51 | pci_devfn_t igd = PCI_DEV(0, 2, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 52 | |
| 53 | /* setup somewhere */ |
| 54 | u8 cmd = pci_read_config8(igd, PCI_COMMAND); |
| 55 | cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 56 | pci_write_config8(igd, PCI_COMMAND, cmd); |
| 57 | void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0); |
| 58 | |
| 59 | /* clear GTT, 2MB is enough (and should be safe) */ |
| 60 | memset(bar, 0, 2<<20); |
| 61 | |
| 62 | /* and now disable again */ |
| 63 | cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 64 | pci_write_config8(igd, PCI_COMMAND, cmd); |
| 65 | pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); |
| 66 | } |
| 67 | |
| 68 | if (stepping == STEPPING_B3) { |
| 69 | MCHBAR8(0xffc) |= 1 << 4; |
Furquan Shaikh | 25f75b2 | 2016-08-29 22:51:41 -0700 | [diff] [blame^] | 70 | pci_devfn_t peg = PCI_DEV(0, 1, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 71 | /* FIXME: proper test? */ |
| 72 | if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { |
| 73 | int val = pci_read_config32(peg, 0xfc) | (1 << 15); |
| 74 | pci_write_config32(peg, 0xfc, val); |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | /* final */ |
| 79 | MCHBAR8(0x94) |= 1 << 3; |
| 80 | } |