northbridge/intel/gm45: transation away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/gm45.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16402
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 0c3c18e..77aba94 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -48,7 +48,7 @@
/* clear GTT */
u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
if (gtt & 0x400) { /* VT mode */
- device_t igd = PCI_DEV(0, 2, 0);
+ pci_devfn_t igd = PCI_DEV(0, 2, 0);
/* setup somewhere */
u8 cmd = pci_read_config8(igd, PCI_COMMAND);
@@ -67,7 +67,7 @@
if (stepping == STEPPING_B3) {
MCHBAR8(0xffc) |= 1 << 4;
- device_t peg = PCI_DEV(0, 1, 0);
+ pci_devfn_t peg = PCI_DEV(0, 1, 0);
/* FIXME: proper test? */
if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
int val = pci_read_config32(peg, 0xfc) | (1 << 15);