Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 2 | |
| 3 | #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H |
| 4 | #define NORTHBRIDGE_INTEL_PINEVIEW_H |
| 5 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 6 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 7 | |
Angel Pons | 24b1d8a | 2021-01-20 12:00:31 +0100 | [diff] [blame^] | 8 | #define DEFAULT_PMIOBAR 0x00000400 |
| 9 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 10 | #define BOOT_PATH_NORMAL 0 |
| 11 | #define BOOT_PATH_RESET 1 |
| 12 | #define BOOT_PATH_RESUME 2 |
| 13 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 14 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 15 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 16 | |
Angel Pons | 0ddc245 | 2020-07-22 11:40:46 +0200 | [diff] [blame] | 17 | #include "hostbridge_regs.h" |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 18 | |
| 19 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 20 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 21 | #define PEGSTS 0x214 /* 32 bits */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 22 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 23 | /* Device 0:2.0 PCI configuration space (Integrated Graphics Device) */ |
| 24 | #define GMCH_IGD PCI_DEV(0, 2, 0) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 25 | |
| 26 | #define GMADR 0x18 |
| 27 | #define GTTADR 0x1c |
| 28 | #define BSM 0x5c |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 29 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 30 | #define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x)) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * MCHBAR |
| 34 | */ |
| 35 | |
Angel Pons | 24b1d8a | 2021-01-20 12:00:31 +0100 | [diff] [blame^] | 36 | #include <northbridge/intel/common/fixed_bars.h> |
| 37 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 38 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 39 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 40 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 41 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 42 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 43 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 44 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 45 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 46 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
| 47 | |
| 48 | /* As there are many registers, define them on a separate file */ |
| 49 | |
| 50 | #include "mchbar_regs.h" |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 51 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 52 | void pineview_early_init(void); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 53 | u32 decode_igd_memory_size(const u32 gms); |
| 54 | u32 decode_igd_gtt_size(const u32 gsm); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 55 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 56 | /* Mainboard romstage callback functions */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 57 | void get_mb_spd_addrmap(u8 *spd_addr_map); |
| 58 | void mb_pirq_setup(void); /* optional */ |
| 59 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 60 | #endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ |