blob: 5e9b7f95bb64ff69ab08cca7a5293f90cda33641 [file] [log] [blame]
Martin Rothf95a11e2022-10-21 16:43:08 -06001# SPDX-License-Identifier: GPL-2.0-only
2
3# TODO: Evaluate what can be moved to a common directory
4# TODO: Update for Glinda
5
6config SOC_AMD_GLINDA
7 bool
Martin Rothf95a11e2022-10-21 16:43:08 -06008 select ACPI_SOC_NVS
Martin Rothf95a11e2022-10-21 16:43:08 -06009 select ARCH_X86
10 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
11 select DRIVERS_USB_ACPI
12 select DRIVERS_USB_PCI_XHCI
13 select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING
14 select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING
15 select FSP_COMPRESS_FSP_S_LZ4
16 select GENERIC_GPIO_LIB
17 select HAVE_ACPI_TABLES
18 select HAVE_CF9_RESET
19 select HAVE_EM100_SUPPORT
20 select HAVE_FSP_GOP
21 select HAVE_SMI_HANDLER
22 select IDT_IN_EVERY_STAGE
Martin Rothbcb610a2022-10-29 13:31:54 -060023 select NO_DDR4
24 select NO_DDR3
25 select NO_DDR2
26 select NO_LPDDR4
Martin Rothf95a11e2022-10-21 16:43:08 -060027 select PARALLEL_MP_AP_WORK
28 select PLATFORM_USES_FSP2_0
29 select PROVIDES_ROM_SHARING
30 select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK
31 select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK
32 select RESET_VECTOR_IN_RAM
33 select RTC
34 select SOC_AMD_COMMON
35 select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct
36 select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct
37 select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct
38 select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct
39 select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct
Felix Held21a5ecd2023-03-07 01:15:42 +010040 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
Martin Rothf95a11e2022-10-21 16:43:08 -060041 select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct
42 select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct
43 select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct
44 select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct
45 select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct
46 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct
Fred Reitberger28908412022-11-01 10:49:16 -040047 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
Martin Rothf95a11e2022-10-21 16:43:08 -060048 select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct
49 select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct
50 select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
51 select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct
52 select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct
53 select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct
54 select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct
55 select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct
56 select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct
57 select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct
58 select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct
59 select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct
60 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct
61 select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct
62 select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct
63 select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct
64 select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
Martin Roth10c43a22023-02-02 17:21:37 -070065 select SOC_AMD_COMMON_BLOCK_RESET
Martin Rothf95a11e2022-10-21 16:43:08 -060066 select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct
67 select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct
68 select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct
69 select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct
Felix Held71375622023-01-12 23:11:54 +010070 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct
Martin Rothf95a11e2022-10-21 16:43:08 -060071 select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct
Felix Held23a398e2023-03-23 23:44:03 +010072 select SOC_AMD_COMMON_BLOCK_SVI3
Felix Helda25117d2023-03-10 00:04:46 +010073 select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # FIXME: This is likely incompatible
Martin Rothf95a11e2022-10-21 16:43:08 -060074 select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct
75 select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct
76 select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
77 select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct
78 select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
Fred Reitbergereb594932023-01-11 15:12:21 -050079 select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
Martin Rothf95a11e2022-10-21 16:43:08 -060080 select SSE2
81 select UDK_2017_BINDING
Martin Rothbcb610a2022-10-29 13:31:54 -060082 select USE_DDR5
Martin Rothf95a11e2022-10-21 16:43:08 -060083 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
84 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
85 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
86 select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
87 select X86_AMD_FIXED_MTRRS
88 select X86_INIT_NEED_1_SIPI
Elyes Haouas3cd06cc2023-01-05 07:42:24 +010089 help
90 AMD Glinda support
91
92if SOC_AMD_GLINDA
Martin Rothf95a11e2022-10-21 16:43:08 -060093
Martin Rothf95a11e2022-10-21 16:43:08 -060094config CHIPSET_DEVICETREE
95 string
96 default "soc/amd/glinda/chipset.cb"
97
98config EARLY_RESERVED_DRAM_BASE
99 hex
100 default 0x2000000
101 help
102 This variable defines the base address of the DRAM which is reserved
103 for usage by coreboot in early stages (i.e. before ramstage is up).
104 This memory gets reserved in BIOS tables to ensure that the OS does
105 not use it, thus preventing corruption of OS memory in case of S3
106 resume.
107
108config EARLYRAM_BSP_STACK_SIZE
109 hex
110 default 0x1000
111
112config PSP_APOB_DRAM_ADDRESS
113 hex
114 default 0x2001000
115 help
116 Location in DRAM where the PSP will copy the AGESA PSP Output
117 Block.
118
119config PSP_APOB_DRAM_SIZE
120 hex
121 default 0x1E000
122
123config PSP_SHAREDMEM_BASE
124 hex
125 default 0x201F000 if VBOOT
126 default 0x0
127 help
128 This variable defines the base address in DRAM memory where PSP copies
129 the vboot workbuf. This is used in the linker script to have a static
130 allocation for the buffer as well as for adding relevant entries in
131 the BIOS directory table for the PSP.
132
133config PSP_SHAREDMEM_SIZE
134 hex
135 default 0x8000 if VBOOT
136 default 0x0
137 help
138 Sets the maximum size for the PSP to pass the vboot workbuf and
139 any logs or timestamps back to coreboot. This will be copied
140 into main memory by the PSP and will be available when the x86 is
141 started. The workbuf's base depends on the address of the reset
142 vector.
143
144config PRE_X86_CBMEM_CONSOLE_SIZE
145 hex
146 default 0x1600
147 help
148 Size of the CBMEM console used in PSP verstage.
149
150config PRERAM_CBMEM_CONSOLE_SIZE
151 hex
152 default 0x1600
153 help
154 Increase this value if preram cbmem console is getting truncated
155
156config CBFS_MCACHE_SIZE
157 hex
158 default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK
159
160config C_ENV_BOOTBLOCK_SIZE
161 hex
162 default 0x10000
163 help
164 Sets the size of the bootblock stage that should be loaded in DRAM.
165 This variable controls the DRAM allocation size in linker script
166 for bootblock stage.
167
168config ROMSTAGE_ADDR
169 hex
170 default 0x2040000
171 help
172 Sets the address in DRAM where romstage should be loaded.
173
174config ROMSTAGE_SIZE
175 hex
176 default 0x80000
177 help
178 Sets the size of DRAM allocation for romstage in linker script.
179
180config FSP_M_ADDR
181 hex
182 default 0x20C0000
183 help
184 Sets the address in DRAM where FSP-M should be loaded. cbfstool
185 performs relocation of FSP-M to this address.
186
187config FSP_M_SIZE
188 hex
189 default 0xC0000
190 help
191 Sets the size of DRAM allocation for FSP-M in linker script.
192
193config FSP_TEMP_RAM_SIZE
194 hex
195 default 0x40000
196 help
197 The amount of coreboot-allocated heap and stack usage by the FSP.
198
199config VERSTAGE_ADDR
200 hex
201 depends on VBOOT_SEPARATE_VERSTAGE
202 default 0x2180000
203 help
204 Sets the address in DRAM where verstage should be loaded if running
205 as a separate stage on x86.
206
207config VERSTAGE_SIZE
208 hex
209 depends on VBOOT_SEPARATE_VERSTAGE
210 default 0x80000
211 help
212 Sets the size of DRAM allocation for verstage in linker script if
213 running as a separate stage on x86.
214
215config ASYNC_FILE_LOADING
216 bool "Loads files from SPI asynchronously"
217 select COOP_MULTITASKING
218 select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
219 select CBFS_PRELOAD
220 help
221 When enabled, the platform will use the LPC SPI DMA controller to
222 asynchronously load contents from the SPI ROM. This will improve
223 boot time because the CPUs can be performing useful work while the
224 SPI contents are being preloaded.
225
226config CBFS_CACHE_SIZE
227 hex
228 default 0x40000 if CBFS_PRELOAD
229
230config RO_REGION_ONLY
231 string
232 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
233 default "apu/amdfw"
234
235config ECAM_MMCONF_BASE_ADDRESS
236 default 0xF8000000
237
238config ECAM_MMCONF_BUS_NUMBER
239 default 64
240
241config MAX_CPUS
242 int
243 default 8 if SOC_AMD_GLINDA
244 default 16
245 help
246 Maximum number of threads the platform can have.
247
248config CONSOLE_UART_BASE_ADDRESS
249 depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
250 hex
251 default 0xfedc9000 if UART_FOR_CONSOLE = 0
252 default 0xfedca000 if UART_FOR_CONSOLE = 1
253 default 0xfedce000 if UART_FOR_CONSOLE = 2
254 default 0xfedcf000 if UART_FOR_CONSOLE = 3
255 default 0xfedd1000 if UART_FOR_CONSOLE = 4
256
257config SMM_TSEG_SIZE
258 hex
259 default 0x800000 if HAVE_SMI_HANDLER
260 default 0x0
261
262config SMM_RESERVED_SIZE
263 hex
264 default 0x180000
265
266config SMM_MODULE_STACK_SIZE
267 hex
268 default 0x800
269
270config ACPI_BERT
271 bool "Build ACPI BERT Table"
272 default y
273 depends on HAVE_ACPI_TABLES
274 help
275 Report Machine Check errors identified in POST to the OS in an
276 ACPI Boot Error Record Table.
277
278config ACPI_BERT_SIZE
279 hex
280 default 0x4000 if ACPI_BERT
281 default 0x0
282 help
283 Specify the amount of DRAM reserved for gathering the data used to
284 generate the ACPI table.
285
286config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
287 int
288 default 150
289
290config DISABLE_SPI_FLASH_ROM_SHARING
291 def_bool n
292 help
293 Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
294 which indicates a board level ROM transaction request. This
295 removes arbitration with board and assumes the chipset controls
296 the SPI flash bus entirely.
297
298config DISABLE_KEYBOARD_RESET_PIN
299 bool
300 help
Martin Roth9ceac742023-02-08 14:26:02 -0700301 Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L.
Martin Rothf95a11e2022-10-21 16:43:08 -0600302
Martin Rothf95a11e2022-10-21 16:43:08 -0600303menu "PSP Configuration Options"
304
305config AMD_FWM_POSITION_INDEX
306 int "Firmware Directory Table location (0 to 5)"
307 range 0 5
308 default 0 if BOARD_ROMSIZE_KB_512
309 default 1 if BOARD_ROMSIZE_KB_1024
310 default 2 if BOARD_ROMSIZE_KB_2048
311 default 3 if BOARD_ROMSIZE_KB_4096
312 default 4 if BOARD_ROMSIZE_KB_8192
313 default 5 if BOARD_ROMSIZE_KB_16384
314 help
315 Typically this is calculated by the ROM size, but there may
316 be situations where you want to put the firmware directory
317 table in a different location.
318 0: 512 KB - 0xFFFA0000
319 1: 1 MB - 0xFFF20000
320 2: 2 MB - 0xFFE20000
321 3: 4 MB - 0xFFC20000
322 4: 8 MB - 0xFF820000
323 5: 16 MB - 0xFF020000
324
325comment "AMD Firmware Directory Table set to location for 512KB ROM"
326 depends on AMD_FWM_POSITION_INDEX = 0
327comment "AMD Firmware Directory Table set to location for 1MB ROM"
328 depends on AMD_FWM_POSITION_INDEX = 1
329comment "AMD Firmware Directory Table set to location for 2MB ROM"
330 depends on AMD_FWM_POSITION_INDEX = 2
331comment "AMD Firmware Directory Table set to location for 4MB ROM"
332 depends on AMD_FWM_POSITION_INDEX = 3
333comment "AMD Firmware Directory Table set to location for 8MB ROM"
334 depends on AMD_FWM_POSITION_INDEX = 4
335comment "AMD Firmware Directory Table set to location for 16MB ROM"
336 depends on AMD_FWM_POSITION_INDEX = 5
337
338config AMDFW_CONFIG_FILE
339 string "AMD PSP Firmware config file"
340 default "src/soc/amd/glinda/fw.cfg"
341 help
342 Specify the path/location of AMD PSP Firmware config file.
343
344config PSP_DISABLE_POSTCODES
345 bool "Disable PSP post codes"
346 help
347 Disables the output of port80 post codes from PSP.
348
349config PSP_POSTCODES_ON_ESPI
350 bool "Use eSPI bus for PSP post codes"
351 default y
352 depends on !PSP_DISABLE_POSTCODES
353 help
354 Select to send PSP port80 post codes on eSPI bus.
355 If not selected, PSP port80 codes will be sent on LPC bus.
356
357config PSP_LOAD_MP2_FW
358 bool
359 default n
360 help
361 Include the MP2 firmwares and configuration into the PSP build.
362
363 If unsure, answer 'n'
364
365config PSP_UNLOCK_SECURE_DEBUG
366 bool "Unlock secure debug"
367 default y
368 help
369 Select this item to enable secure debug options in PSP.
370
371config HAVE_PSP_WHITELIST_FILE
372 bool "Include a debug whitelist file in PSP build"
373 default n
374 help
375 Support secured unlock prior to reset using a whitelisted
376 serial number. This feature requires a signed whitelist image
377 and bootloader from AMD.
378
379 If unsure, answer 'n'
380
381config PSP_WHITELIST_FILE
382 string "Debug whitelist file path"
383 depends on HAVE_PSP_WHITELIST_FILE
384 default "site-local/3rdparty/amd_blobs/glinda/PSP/wtl-mrg.sbin"
385
386config HAVE_SPL_FILE
387 bool "Have a mainboard specific SPL table file"
388 default n
389 help
390 Have a mainboard specific Security Patch Level (SPL) table file. SPL file
391 is required to support PSP FW anti-rollback and needs to be created by AMD.
392 The default SPL file applies to all boards that use the concerned SoC and
393 is dropped under 3rdparty/blobs. The mainboard specific SPL file override
394 can be applied through SPL_TABLE_FILE config.
395
396 If unsure, answer 'n'
397
398config SPL_TABLE_FILE
399 string "SPL table file"
400 depends on HAVE_SPL_FILE
401 default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin"
402
403config HAVE_SPL_RW_AB_FILE
404 bool "Have a separate mainboard-specific SPL file in RW A/B partitions"
405 default n
406 depends on HAVE_SPL_FILE
407 depends on VBOOT_SLOTS_RW_AB
408 help
409 Have separate mainboard-specific Security Patch Level (SPL) table
410 file for the RW A/B FMAP partitions. See the help text of
411 HAVE_SPL_FILE for a more detailed description.
412
413config SPL_RW_AB_TABLE_FILE
414 string "Separate SPL table file for RW A/B partitions"
415 depends on HAVE_SPL_RW_AB_FILE
416 default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MRG.sbin"
417
418config PSP_SOFTFUSE_BITS
419 string "PSP Soft Fuse bits to enable"
420 default "34 28 6"
421 help
422 Space separated list of Soft Fuse bits to enable.
423 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
424 Bit 7: Disable PSP postcodes on Renoir and newer chips only
425 (Set by PSP_DISABLE_PORT80)
426 Bit 15: PSP debug output destination:
427 0=SoC MMIO UART, 1=IO port 0x3F8
428 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
429
430 See #55758 (NDA) for additional bit definitions.
431
432config PSP_VERSTAGE_FILE
433 string "Specify the PSP_verstage file path"
434 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
435 default "\$(obj)/psp_verstage.bin"
436 help
437 Add psp_verstage file to the build & PSP Directory Table
438
439config PSP_VERSTAGE_SIGNING_TOKEN
440 string "Specify the PSP_verstage Signature Token file path"
441 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
442 default ""
443 help
444 Add psp_verstage signature token to the build & PSP Directory Table
445
446endmenu
447
448config VBOOT
449 select VBOOT_VBNV_CMOS
450 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
451
452config VBOOT_STARTS_BEFORE_BOOTBLOCK
453 def_bool n
454 depends on VBOOT
455 select ARCH_VERSTAGE_ARMV7
456 help
457 Runs verstage on the PSP. Only available on
458 certain ChromeOS branded parts from AMD.
459
460config VBOOT_HASH_BLOCK_SIZE
461 hex
462 default 0x9000
463 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
464 help
465 Because the bulk of the time in psp_verstage to hash the RO cbfs is
466 spent in the overhead of doing svc calls, increasing the hash block
467 size significantly cuts the verstage hashing time as seen below.
468
469 4k takes 180ms
470 16k takes 44ms
471 32k takes 33.7ms
472 36k takes 32.5ms
473 There's actually still room for an even bigger stack, but we've
474 reached a point of diminishing returns.
475
476config CMOS_RECOVERY_BYTE
477 hex
478 default 0x51
479 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
480 help
481 If the workbuf is not passed from the PSP to coreboot, set the
482 recovery flag and reboot. The PSP will read this byte, mark the
483 recovery request in VBNV, and reset the system into recovery mode.
484
485 This is the byte before the default first byte used by VBNV
486 (0x26 + 0x0E - 1)
487
488if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
489
490config RWA_REGION_ONLY
491 string
492 default "apu/amdfw_a"
493 help
494 Add a space-delimited list of filenames that should only be in the
495 RW-A section.
496
497config RWB_REGION_ONLY
498 string
499 default "apu/amdfw_b"
500 help
501 Add a space-delimited list of filenames that should only be in the
502 RW-B section.
503
504endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
505
506endif # SOC_AMD_REMBRANDT_BASE