| Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | |
| Varun Joshi | 2255eba | 2020-03-31 18:02:33 -0700 | [diff] [blame^] | 3 | # PCIe Port 8 for LAN |
| 4 | register "PcieRpEnable[7]" = "1" |
| 5 | register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" |
| 6 | register "PcieClkSrcClkReq[3]" = "3" |
| 7 | |
| Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 8 | device domain 0 on |
| Varun Joshi | 2255eba | 2020-03-31 18:02:33 -0700 | [diff] [blame^] | 9 | device pci 1f.6 on end # GbE 0x15FC |
| Bora Guvendik | 3a1a037 | 2020-03-09 18:20:07 -0700 | [diff] [blame] | 10 | end |
| 11 | |
| 12 | end |