Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 16 | #include <delay.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 21 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 23 | #include <soc/ramstage.h> |
| 24 | #include <soc/xhci.h> |
| 25 | #include <soc/cpu.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 26 | |
| 27 | #ifdef __SMM__ |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 28 | static u8 *usb_xhci_mem_base(pci_devfn_t dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | { |
| 30 | u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 31 | |
| 32 | /* Check if the controller is disabled or not present */ |
| 33 | if (mem_base == 0 || mem_base == 0xffffffff) |
| 34 | return 0; |
| 35 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 36 | return (u8 *)(mem_base & ~0xf); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 37 | } |
| 38 | |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 39 | static int usb_xhci_port_count_usb3(pci_devfn_t dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 40 | { |
| 41 | /* PCH-LP has 4 SS ports */ |
| 42 | return 4; |
| 43 | } |
| 44 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 45 | static void usb_xhci_reset_status_usb3(u8 *mem_base, int port) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 46 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 47 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 48 | u32 status = read32(portsc); |
| 49 | /* Do not set Port Enabled/Disabled field */ |
| 50 | status &= ~XHCI_USB3_PORTSC_PED; |
| 51 | /* Clear all change status bits */ |
| 52 | status |= XHCI_USB3_PORTSC_CHST; |
| 53 | write32(portsc, status); |
| 54 | } |
| 55 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 56 | static void usb_xhci_reset_port_usb3(u8 *mem_base, int port) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 57 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 58 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 59 | write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); |
| 60 | } |
| 61 | |
| 62 | #define XHCI_RESET_DELAY_US 1000 /* 1ms */ |
| 63 | #define XHCI_RESET_TIMEOUT 100 /* 100ms */ |
| 64 | |
| 65 | /* |
| 66 | * 1) Wait until port is done polling |
| 67 | * 2) If port is disconnected |
| 68 | * a) Issue warm port reset |
| 69 | * b) Poll for warm reset complete |
| 70 | * c) Write 1 to port change status bits |
| 71 | */ |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 72 | static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 73 | { |
| 74 | u32 status, port_disabled; |
| 75 | int timeout, port; |
| 76 | int port_count = usb_xhci_port_count_usb3(dev); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 77 | u8 *mem_base = usb_xhci_mem_base(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 78 | |
| 79 | if (!mem_base || !port_count) |
| 80 | return; |
| 81 | |
| 82 | /* Get mask of disabled ports */ |
| 83 | port_disabled = pci_read_config32(dev, XHCI_USB3PDO); |
| 84 | |
| 85 | /* Wait until all enabled ports are done polling */ |
| 86 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 87 | int complete = 1; |
| 88 | for (port = 0; port < port_count; port++) { |
| 89 | /* Skip disabled ports */ |
| 90 | if (port_disabled & (1 << port)) |
| 91 | continue; |
| 92 | /* Read port link status field */ |
| 93 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 94 | status &= XHCI_USB3_PORTSC_PLS; |
| 95 | if (status == XHCI_PLSR_POLLING) |
| 96 | complete = 0; |
| 97 | } |
| 98 | /* Exit if all ports not polling */ |
| 99 | if (complete) |
| 100 | break; |
| 101 | udelay(XHCI_RESET_DELAY_US); |
| 102 | } |
| 103 | |
| 104 | /* Reset all requested ports */ |
| 105 | for (port = 0; port < port_count; port++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 106 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 107 | /* Skip disabled ports */ |
| 108 | if (port_disabled & (1 << port)) |
| 109 | continue; |
| 110 | status = read32(portsc) & XHCI_USB3_PORTSC_PLS; |
| 111 | /* Reset all or only disconnected ports */ |
| 112 | if (all || (status == XHCI_PLSR_RXDETECT || |
| 113 | status == XHCI_PLSR_POLLING)) |
| 114 | usb_xhci_reset_port_usb3(mem_base, port); |
| 115 | else |
| 116 | port_disabled |= 1 << port; |
| 117 | } |
| 118 | |
| 119 | /* Wait for warm reset complete on all reset ports */ |
| 120 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 121 | int complete = 1; |
| 122 | for (port = 0; port < port_count; port++) { |
| 123 | /* Only check ports that were reset */ |
| 124 | if (port_disabled & (1 << port)) |
| 125 | continue; |
| 126 | /* Check if warm reset is complete */ |
| 127 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 128 | if (!(status & XHCI_USB3_PORTSC_WRC)) |
| 129 | complete = 0; |
| 130 | } |
| 131 | /* Check for warm reset complete in any port */ |
| 132 | if (complete) |
| 133 | break; |
| 134 | udelay(XHCI_RESET_DELAY_US); |
| 135 | } |
| 136 | |
| 137 | /* Clear port change status bits */ |
| 138 | for (port = 0; port < port_count; port++) |
| 139 | usb_xhci_reset_status_usb3(mem_base, port); |
| 140 | } |
| 141 | |
| 142 | /* Handler for XHCI controller on entry to S3/S4/S5 */ |
Elyes HAOUAS | 4658a98 | 2018-09-20 08:46:35 +0200 | [diff] [blame] | 143 | void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 144 | { |
| 145 | u16 reg16; |
| 146 | u32 reg32; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 147 | u8 *mem_base = usb_xhci_mem_base(dev); |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 148 | u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 149 | |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 150 | if (!mem_base || slp_typ < ACPI_S3) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 151 | return; |
| 152 | |
| 153 | /* Set D0 state */ |
| 154 | reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); |
| 155 | reg16 &= ~XHCI_PWR_CTL_SET_MASK; |
| 156 | reg16 |= XHCI_PWR_CTL_SET_D0; |
| 157 | pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); |
| 158 | |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 159 | if (!is_broadwell) { |
| 160 | /* This WA is only for lpt */ |
| 161 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 162 | /* Clear PCI 0xB0[14:13] */ |
| 163 | reg32 = pci_read_config32(dev, 0xb0); |
| 164 | reg32 &= ~((1 << 14) | (1 << 13)); |
| 165 | pci_write_config32(dev, 0xb0, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 166 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 167 | /* Clear MMIO 0x816c[14,2] */ |
| 168 | reg32 = read32(mem_base + 0x816c); |
| 169 | reg32 &= ~((1 << 14) | (1 << 2)); |
| 170 | write32(mem_base + 0x816c, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 171 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 172 | /* Reset disconnected USB3 ports */ |
| 173 | usb_xhci_reset_usb3(dev, 0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 174 | |
Patrick Georgi | 46d3ac1 | 2015-04-20 10:27:59 +0200 | [diff] [blame] | 175 | /* Set MMIO 0x80e0[15] */ |
| 176 | reg32 = read32(mem_base + 0x80e0); |
| 177 | reg32 |= (1 << 15); |
| 178 | write32(mem_base + 0x80e0, reg32); |
Todd Broch | df4081e | 2015-02-06 17:13:53 -0800 | [diff] [blame] | 179 | } else { |
| 180 | /* |
| 181 | * Clear port change status bits. Clearing CSC alone seemed to |
| 182 | * fix wakeup from S3 if entering USB compliance state even if |
| 183 | * bit wasn't set on the port. |
| 184 | */ |
| 185 | int port; |
| 186 | for (port = 0; port < usb_xhci_port_count_usb3(dev); port++) |
| 187 | usb_xhci_reset_status_usb3(mem_base, port); |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | reg32 = read32(mem_base + 0x8154); |
| 191 | reg32 &= ~(1 << 31); |
| 192 | write32(mem_base + 0x8154, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 193 | |
| 194 | /* Set D3Hot state and enable PME */ |
| 195 | pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_SET_D3); |
| 196 | pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_STATUS_PME); |
| 197 | pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_ENABLE_PME); |
| 198 | } |
| 199 | #else /* !__SMM__ */ |
| 200 | |
Duncan Laurie | aafdddf | 2015-02-19 16:21:10 -0800 | [diff] [blame] | 201 | static void xhci_init(struct device *dev) |
| 202 | { |
| 203 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 204 | u16 reg16; |
| 205 | u32 reg32; |
| 206 | |
| 207 | /* Ensure controller is in D0 state */ |
| 208 | reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); |
| 209 | reg16 &= ~XHCI_PWR_CTL_SET_MASK; |
| 210 | reg16 |= XHCI_PWR_CTL_SET_D0; |
| 211 | pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); |
| 212 | |
| 213 | /* Disable Compliance Mode Entry */ |
| 214 | reg32 = read32(res2mmio(res, 0x80ec, 0)); |
| 215 | reg32 |= (1 << 0); |
| 216 | write32(res2mmio(res, 0x80ec, 0), reg32); |
| 217 | } |
| 218 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 219 | static struct device_operations usb_xhci_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 220 | .read_resources = pci_dev_read_resources, |
| 221 | .set_resources = pci_dev_set_resources, |
| 222 | .enable_resources = pci_dev_enable_resources, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 223 | .ops_pci = &broadwell_pci_ops, |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 224 | .init = xhci_init, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 225 | }; |
| 226 | |
| 227 | static const unsigned short pci_device_ids[] = { |
| 228 | 0x9c31, /* LynxPoint-LP */ |
| 229 | 0x9cb1, /* WildcatPoint */ |
| 230 | 0 |
| 231 | }; |
| 232 | |
| 233 | static const struct pci_driver pch_usb_xhci __pci_driver = { |
| 234 | .ops = &usb_xhci_ops, |
| 235 | .vendor = PCI_VENDOR_ID_INTEL, |
| 236 | .devices = pci_device_ids, |
| 237 | }; |
| 238 | #endif /* !__SMM__ */ |