Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s5_enable_ac" = "0" |
| 5 | register "deep_s5_enable_dc" = "0" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | # GPE configuration |
| 9 | # Note that GPE events called out in ASL code rely on this |
| 10 | # route. i.e. If this route changes then the affected GPE |
| 11 | # offset bits also need to be changed. |
| 12 | register "gpe0_dw0" = "GPP_B" |
| 13 | register "gpe0_dw1" = "GPP_D" |
| 14 | register "gpe0_dw2" = "GPP_E" |
| 15 | |
| 16 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 17 | register "gen1_dec" = "0x00fc0801" |
| 18 | |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 19 | # Enable DPTF |
| 20 | register "dptf_enable" = "1" |
| 21 | |
| 22 | # FSP Configuration |
Angel Pons | e8c8283 | 2020-07-26 17:21:57 +0200 | [diff] [blame] | 23 | register "IoBufferOwnership" = "0" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 24 | register "ScsEmmcHs400Enabled" = "1" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 25 | register "SkipExtGfxScan" = "1" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 26 | register "SaGv" = "SaGv_Enabled" |
Michael Niewöhner | 6238563 | 2019-09-23 14:38:41 +0200 | [diff] [blame] | 27 | register "PchHdaVcType" = "Vc1" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 28 | |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 29 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 30 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 31 | register "PmConfigSlpS3MinAssert" = "2" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 32 | |
| 33 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 34 | register "PmConfigSlpS4MinAssert" = "4" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 35 | |
| 36 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 37 | register "PmConfigSlpSusMinAssert" = "3" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 38 | |
| 39 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 40 | register "PmConfigSlpAMinAssert" = "3" |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 41 | |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 42 | |
| 43 | # VR Settings Configuration for 4 Domains |
| 44 | #+----------------+-------+-------+-------+-------+ |
| 45 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 46 | #+----------------+-------+-------+-------+-------+ |
| 47 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
Wim Vervoorn | 57aa8e3 | 2019-12-06 11:30:33 +0100 | [diff] [blame] | 48 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 49 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 50 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 51 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 52 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 53 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 54 | #| IccMax | 7A | 34A | 35A | 35A | |
| 55 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 56 | #+----------------+-------+-------+-------+-------+ |
| 57 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 58 | .vr_config_enable = 1, |
| 59 | .psi1threshold = VR_CFG_AMP(20), |
| 60 | .psi2threshold = VR_CFG_AMP(4), |
| 61 | .psi3threshold = VR_CFG_AMP(1), |
| 62 | .psi3enable = 1, |
| 63 | .psi4enable = 1, |
| 64 | .imon_slope = 0, |
| 65 | .imon_offset = 0, |
| 66 | .icc_max = VR_CFG_AMP(7), |
| 67 | .voltage_limit = 1520 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 68 | }" |
| 69 | |
| 70 | register "domain_vr_config[VR_IA_CORE]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 71 | .vr_config_enable = 1, |
| 72 | .psi1threshold = VR_CFG_AMP(20), |
| 73 | .psi2threshold = VR_CFG_AMP(5), |
| 74 | .psi3threshold = VR_CFG_AMP(1), |
| 75 | .psi3enable = 1, |
| 76 | .psi4enable = 1, |
| 77 | .imon_slope = 0, |
| 78 | .imon_offset = 0, |
| 79 | .icc_max = VR_CFG_AMP(34), |
| 80 | .voltage_limit = 1520 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 81 | }" |
| 82 | |
| 83 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 84 | .vr_config_enable = 1, |
| 85 | .psi1threshold = VR_CFG_AMP(20), |
| 86 | .psi2threshold = VR_CFG_AMP(5), |
| 87 | .psi3threshold = VR_CFG_AMP(1), |
| 88 | .psi3enable = 1, |
| 89 | .psi4enable = 1, |
| 90 | .imon_slope = 0, |
| 91 | .imon_offset = 0, |
| 92 | .icc_max = VR_CFG_AMP(35), |
| 93 | .voltage_limit = 1520 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 94 | }" |
| 95 | |
| 96 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 97 | .vr_config_enable = 1, |
| 98 | .psi1threshold = VR_CFG_AMP(20), |
| 99 | .psi2threshold = VR_CFG_AMP(5), |
| 100 | .psi3threshold = VR_CFG_AMP(1), |
| 101 | .psi3enable = 1, |
| 102 | .psi4enable = 1, |
| 103 | .imon_slope = 0, |
| 104 | .imon_offset = 0, |
| 105 | .icc_max = VR_CFG_AMP(35), |
| 106 | .voltage_limit = 1520 |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 107 | }" |
| 108 | |
| 109 | # Send an extra VR mailbox command for the PS4 exit issue |
| 110 | register "SendVrMbxCmd" = "2" |
| 111 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 112 | device cpu_cluster 0 on end |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 113 | device domain 0 on |
| 114 | device pci 00.0 on end # Host Bridge |
| 115 | device pci 02.0 on end # Integrated Graphics Device |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 116 | device pci 04.0 on end # SA thermal subsystem |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 117 | device pci 14.0 on end # USB xHCI |
| 118 | device pci 14.1 off end # USB xDCI (OTG) |
| 119 | device pci 14.2 on end # Thermal Subsystem |
| 120 | device pci 15.0 on end # I2C #0 |
| 121 | device pci 15.1 on end # I2C #1 |
| 122 | device pci 15.2 on end # I2C #2 |
| 123 | device pci 15.3 on end # I2C #3 |
| 124 | device pci 16.0 on end # Management Engine Interface 1 |
| 125 | device pci 16.1 off end # Management Engine Interface 2 |
| 126 | device pci 16.2 off end # Management Engine IDE-R |
| 127 | device pci 16.3 off end # Management Engine KT Redirection |
| 128 | device pci 16.4 off end # Management Engine Interface 3 |
| 129 | device pci 17.0 off end # SATA |
| 130 | device pci 19.0 on end # UART #2 |
| 131 | device pci 19.1 off end # I2C #5 |
| 132 | device pci 19.2 on end # I2C #4 |
| 133 | device pci 1c.0 on end # PCI Express Port 1 |
| 134 | device pci 1c.1 off end # PCI Express Port 2 |
| 135 | device pci 1c.2 off end # PCI Express Port 3 |
| 136 | device pci 1c.3 off end # PCI Express Port 4 |
| 137 | device pci 1c.4 off end # PCI Express Port 5 |
| 138 | device pci 1c.5 off end # PCI Express Port 6 |
| 139 | device pci 1c.6 off end # PCI Express Port 7 |
| 140 | device pci 1c.7 off end # PCI Express Port 8 |
| 141 | device pci 1d.0 on end # PCI Express Port 9 |
| 142 | device pci 1d.1 off end # PCI Express Port 10 |
| 143 | device pci 1d.2 off end # PCI Express Port 11 |
| 144 | device pci 1d.3 off end # PCI Express Port 12 |
| 145 | device pci 1e.0 on end # UART #0 |
| 146 | device pci 1e.1 off end # UART #1 |
| 147 | device pci 1e.2 off end # GSPI #0 |
| 148 | device pci 1e.3 off end # GSPI #1 |
| 149 | device pci 1e.4 on end # eMMC |
| 150 | device pci 1e.5 off end # SDIO |
| 151 | device pci 1e.6 on end # SDCard |
| 152 | device pci 1f.0 on end # LPC Interface |
| 153 | device pci 1f.1 on end # P2SB |
| 154 | device pci 1f.2 on end # Power Management Controller |
Felix Singer | 048d9b5 | 2020-07-25 14:31:58 +0200 | [diff] [blame] | 155 | device pci 1f.3 off end # Intel HDA |
Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame] | 156 | device pci 1f.4 on end # SMBus |
| 157 | device pci 1f.5 on end # PCH SPI |
| 158 | device pci 1f.6 off end # GbE |
| 159 | end |
| 160 | end |