Praveen hodagatta pranesh | 7e48b47 | 2019-01-04 01:10:25 +0800 | [diff] [blame^] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s5_enable_ac" = "0" |
| 5 | register "deep_s5_enable_dc" = "0" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | # GPE configuration |
| 9 | # Note that GPE events called out in ASL code rely on this |
| 10 | # route. i.e. If this route changes then the affected GPE |
| 11 | # offset bits also need to be changed. |
| 12 | register "gpe0_dw0" = "GPP_B" |
| 13 | register "gpe0_dw1" = "GPP_D" |
| 14 | register "gpe0_dw2" = "GPP_E" |
| 15 | |
| 16 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 17 | register "gen1_dec" = "0x00fc0801" |
| 18 | |
| 19 | # Enable "Intel Speed Shift Technology" |
| 20 | register "speed_shift_enable" = "1" |
| 21 | |
| 22 | # Enable DPTF |
| 23 | register "dptf_enable" = "1" |
| 24 | |
| 25 | # FSP Configuration |
| 26 | register "SmbusEnable" = "1" |
| 27 | register "ScsEmmcEnabled" = "1" |
| 28 | register "ScsEmmcHs400Enabled" = "1" |
| 29 | register "ScsSdCardEnabled" = "2" |
| 30 | register "InternalGfx" = "1" |
| 31 | register "SkipExtGfxScan" = "1" |
| 32 | register "Device4Enable" = "1" |
| 33 | register "SaGv" = "SaGv_Enabled" |
| 34 | |
| 35 | register "pirqa_routing" = "PCH_IRQ11" |
| 36 | register "pirqb_routing" = "PCH_IRQ10" |
| 37 | register "pirqc_routing" = "PCH_IRQ11" |
| 38 | register "pirqd_routing" = "PCH_IRQ11" |
| 39 | register "pirqe_routing" = "PCH_IRQ11" |
| 40 | register "pirqf_routing" = "PCH_IRQ11" |
| 41 | register "pirqg_routing" = "PCH_IRQ11" |
| 42 | register "pirqh_routing" = "PCH_IRQ11" |
| 43 | |
| 44 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 45 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 46 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 47 | |
| 48 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 49 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 50 | |
| 51 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 52 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 53 | |
| 54 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 55 | register "PmConfigSlpAMinAssert" = "0x03" |
| 56 | |
| 57 | # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled |
| 58 | register "SerialIrqConfigSirqEnable" = "0x01" |
| 59 | |
| 60 | # VR Settings Configuration for 4 Domains |
| 61 | #+----------------+-------+-------+-------+-------+ |
| 62 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 63 | #+----------------+-------+-------+-------+-------+ |
| 64 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 65 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 66 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 67 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 68 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 69 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 70 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 71 | #| IccMax | 7A | 34A | 35A | 35A | |
| 72 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 73 | #+----------------+-------+-------+-------+-------+ |
| 74 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 75 | .vr_config_enable = 1, \ |
| 76 | .psi1threshold = 0x50, \ |
| 77 | .psi2threshold = 0x10, \ |
| 78 | .psi3threshold = 0x4, \ |
| 79 | .psi3enable = 1, \ |
| 80 | .psi4enable = 1, \ |
| 81 | .imon_slope = 0x0, \ |
| 82 | .imon_offset = 0x0, \ |
| 83 | .icc_max = 0x1C, \ |
| 84 | .voltage_limit = 0x5F0 \ |
| 85 | }" |
| 86 | |
| 87 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 88 | .vr_config_enable = 1, \ |
| 89 | .psi1threshold = 0x50, \ |
| 90 | .psi2threshold = 0x14, \ |
| 91 | .psi3threshold = 0x4, \ |
| 92 | .psi3enable = 1, \ |
| 93 | .psi4enable = 1, \ |
| 94 | .imon_slope = 0x0, \ |
| 95 | .imon_offset = 0x0, \ |
| 96 | .icc_max = 0x88, \ |
| 97 | .voltage_limit = 0x5F0 \ |
| 98 | }" |
| 99 | |
| 100 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 101 | .vr_config_enable = 1, \ |
| 102 | .psi1threshold = 0x50, \ |
| 103 | .psi2threshold = 0x14, \ |
| 104 | .psi3threshold = 0x4, \ |
| 105 | .psi3enable = 1, \ |
| 106 | .psi4enable = 1, \ |
| 107 | .imon_slope = 0x0, \ |
| 108 | .imon_offset = 0x0, \ |
| 109 | .icc_max = 0x8C ,\ |
| 110 | .voltage_limit = 0x5F0 \ |
| 111 | }" |
| 112 | |
| 113 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 114 | .vr_config_enable = 1, \ |
| 115 | .psi1threshold = 0x50, \ |
| 116 | .psi2threshold = 0x14, \ |
| 117 | .psi3threshold = 0x4, \ |
| 118 | .psi3enable = 1, \ |
| 119 | .psi4enable = 1, \ |
| 120 | .imon_slope = 0x0, \ |
| 121 | .imon_offset = 0x0, \ |
| 122 | .icc_max = 0x8C, \ |
| 123 | .voltage_limit = 0x5F0 \ |
| 124 | }" |
| 125 | |
| 126 | # Send an extra VR mailbox command for the PS4 exit issue |
| 127 | register "SendVrMbxCmd" = "2" |
| 128 | |
| 129 | # Enable/Disable VMX feature |
| 130 | register "VmxEnable" = "0" |
| 131 | |
| 132 | device cpu_cluster 0 on |
| 133 | device lapic 0 on end |
| 134 | end |
| 135 | device domain 0 on |
| 136 | device pci 00.0 on end # Host Bridge |
| 137 | device pci 02.0 on end # Integrated Graphics Device |
| 138 | device pci 14.0 on end # USB xHCI |
| 139 | device pci 14.1 off end # USB xDCI (OTG) |
| 140 | device pci 14.2 on end # Thermal Subsystem |
| 141 | device pci 15.0 on end # I2C #0 |
| 142 | device pci 15.1 on end # I2C #1 |
| 143 | device pci 15.2 on end # I2C #2 |
| 144 | device pci 15.3 on end # I2C #3 |
| 145 | device pci 16.0 on end # Management Engine Interface 1 |
| 146 | device pci 16.1 off end # Management Engine Interface 2 |
| 147 | device pci 16.2 off end # Management Engine IDE-R |
| 148 | device pci 16.3 off end # Management Engine KT Redirection |
| 149 | device pci 16.4 off end # Management Engine Interface 3 |
| 150 | device pci 17.0 off end # SATA |
| 151 | device pci 19.0 on end # UART #2 |
| 152 | device pci 19.1 off end # I2C #5 |
| 153 | device pci 19.2 on end # I2C #4 |
| 154 | device pci 1c.0 on end # PCI Express Port 1 |
| 155 | device pci 1c.1 off end # PCI Express Port 2 |
| 156 | device pci 1c.2 off end # PCI Express Port 3 |
| 157 | device pci 1c.3 off end # PCI Express Port 4 |
| 158 | device pci 1c.4 off end # PCI Express Port 5 |
| 159 | device pci 1c.5 off end # PCI Express Port 6 |
| 160 | device pci 1c.6 off end # PCI Express Port 7 |
| 161 | device pci 1c.7 off end # PCI Express Port 8 |
| 162 | device pci 1d.0 on end # PCI Express Port 9 |
| 163 | device pci 1d.1 off end # PCI Express Port 10 |
| 164 | device pci 1d.2 off end # PCI Express Port 11 |
| 165 | device pci 1d.3 off end # PCI Express Port 12 |
| 166 | device pci 1e.0 on end # UART #0 |
| 167 | device pci 1e.1 off end # UART #1 |
| 168 | device pci 1e.2 off end # GSPI #0 |
| 169 | device pci 1e.3 off end # GSPI #1 |
| 170 | device pci 1e.4 on end # eMMC |
| 171 | device pci 1e.5 off end # SDIO |
| 172 | device pci 1e.6 on end # SDCard |
| 173 | device pci 1f.0 on end # LPC Interface |
| 174 | device pci 1f.1 on end # P2SB |
| 175 | device pci 1f.2 on end # Power Management Controller |
| 176 | device pci 1f.3 on end # Intel HDA |
| 177 | device pci 1f.4 on end # SMBus |
| 178 | device pci 1f.5 on end # PCH SPI |
| 179 | device pci 1f.6 off end # GbE |
| 180 | end |
| 181 | end |