Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 2 | |
| 3 | chip soc/intel/skylake |
| 4 | |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 5 | register "deep_sx_config" = "DSX_EN_WAKE_PIN" |
| 6 | |
| 7 | register "eist_enable" = "1" |
| 8 | |
| 9 | # GPE configuration |
| 10 | # Note that GPE events called out in ASL code rely on this |
| 11 | # route. i.e. If this route changes then the affected GPE |
| 12 | # offset bits also need to be changed. |
| 13 | register "gpe0_dw0" = "GPP_B" |
| 14 | register "gpe0_dw1" = "GPP_D" |
| 15 | register "gpe0_dw2" = "GPP_E" |
| 16 | |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 17 | # Enable DPTF |
| 18 | register "dptf_enable" = "1" |
| 19 | |
| 20 | # FSP Configuration |
Maxim Polyakov | 0de6c50 | 2019-04-03 00:44:28 +0300 | [diff] [blame] | 21 | register "PrimaryDisplay" = "Display_PEG" |
Maxim Polyakov | e6a491e | 2019-06-26 11:17:37 +0300 | [diff] [blame] | 22 | |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 23 | # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 24 | # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| 25 | register "PmConfigSlpS3MinAssert" = "0x02" |
| 26 | |
| 27 | # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| 28 | register "PmConfigSlpS4MinAssert" = "0x04" |
| 29 | |
| 30 | # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| 31 | register "PmConfigSlpSusMinAssert" = "0x03" |
| 32 | |
| 33 | # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| 34 | register "PmConfigSlpAMinAssert" = "0x03" |
| 35 | |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 36 | # PL2 override 91W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 37 | register "power_limits_config" = "{ |
| 38 | .tdp_pl2_override = 91, |
| 39 | }" |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 40 | |
| 41 | # Send an extra VR mailbox command for the PS4 exit issue |
| 42 | register "SendVrMbxCmd" = "2" |
| 43 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 44 | device cpu_cluster 0 on end |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 45 | device domain 0 on |
| 46 | device pci 00.0 on # Host Bridge |
| 47 | subsystemid 0x1849 0x191f |
| 48 | end |
| 49 | device pci 01.0 on # PEG |
| 50 | subsystemid 0x1849 0x1901 |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 51 | register "Peg0MaxLinkWidth" = "Peg0_x16" |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 52 | |
| 53 | # Configure PCIe clockgen in PCH |
| 54 | register "PcieRpClkReqSupport[0]" = "1" |
| 55 | register "PcieRpClkReqNumber[0]" = "0" |
| 56 | register "PcieRpClkSrcNumber[0]" = "0" |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 57 | end |
| 58 | device pci 02.0 on # Integrated Graphics Device |
| 59 | subsystemid 0x1849 0x1912 |
| 60 | end |
Maxim Polyakov | 0da148e | 2020-08-08 12:22:10 +0300 | [diff] [blame] | 61 | device pci 04.0 on end # Thermal Subsystem |
Maxim Polyakov | 59613ee | 2019-08-23 15:16:12 +0300 | [diff] [blame] | 62 | device pci 08.0 off end # Gaussian Mixture Model |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 63 | device pci 14.0 on # USB xHCI |
| 64 | subsystemid 0x1849 0xa131 |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 65 | |
| 66 | register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" |
| 67 | register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" |
| 68 | register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" |
| 69 | register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" |
| 70 | register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" |
| 71 | register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" |
| 72 | register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" |
| 73 | register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" |
| 74 | register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" |
| 75 | register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" |
| 76 | register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" |
| 77 | register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" |
| 78 | register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" |
| 79 | register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" |
| 80 | |
| 81 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" |
| 82 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" |
| 83 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" |
| 84 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" |
| 85 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" |
| 86 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" |
| 87 | register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 88 | register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 89 | register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| 90 | register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 91 | end |
| 92 | device pci 14.1 off end # USB xDCI (OTG) |
| 93 | device pci 14.2 on # Thermal Subsystem |
| 94 | subsystemid 0x1849 0xa131 |
| 95 | end |
| 96 | device pci 15.0 off end # I2C #0 |
| 97 | device pci 15.1 off end # I2C #1 |
| 98 | device pci 15.2 off end # I2C #2 |
| 99 | device pci 15.3 off end # I2C #3 |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 100 | device pci 16.0 on # Management Engine Interface 1 |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 101 | subsystemid 0x1849 0xa131 |
| 102 | end |
| 103 | device pci 16.1 off end # Management Engine Interface 2 |
| 104 | device pci 16.2 off end # Management Engine IDE-R |
| 105 | device pci 16.3 off end # Management Engine KT Redirection |
| 106 | device pci 16.4 off end # Management Engine Interface 3 |
| 107 | device pci 17.0 on # SATA |
| 108 | subsystemid 0x1849 0xa102 |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 109 | register "SataSalpSupport" = "1" |
| 110 | # SATA4 and SATA5 are located in the lower right corner of the board, |
| 111 | # but they are not populated. This is because the same PCB is used to |
| 112 | # make boards with better PCHs, which can have up to six SATA ports. |
| 113 | # However, the H110 PCH only has four SATA ports, which explains why |
| 114 | # two connectors are missing. |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame^] | 115 | register "SataPortsEnable" = "{ |
| 116 | [0] = 1, |
| 117 | [1] = 1, |
| 118 | [2] = 1, |
| 119 | [3] = 1, |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 120 | }" |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 121 | end |
| 122 | device pci 19.0 off end # UART #2 |
| 123 | device pci 19.1 off end # I2C #5 |
| 124 | device pci 19.2 off end # I2C #4 |
| 125 | device pci 1c.0 on end # PCI Express Port 1 |
| 126 | device pci 1c.1 off end # PCI Express Port 2 |
| 127 | device pci 1c.2 off end # PCI Express Port 3 |
| 128 | device pci 1c.3 off end # PCI Express Port 4 |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 129 | device pci 1c.4 on # PCI Express Port 5 - PCIE slot |
| 130 | register "PcieRpEnable[4]" = "1" |
| 131 | register "PcieRpClkReqSupport[4]" = "1" |
| 132 | register "PcieRpClkReqNumber[4]" = "2" |
| 133 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 134 | register "PcieRpLtrEnable[4]" = "1" |
| 135 | register "PcieRpClkSrcNumber[4]" = "2" |
| 136 | register "PcieRpHotPlug[4]" = "1" |
| 137 | end |
| 138 | device pci 1c.5 on # PCI Express Port 6 - Onboard LAN |
| 139 | register "PcieRpEnable[5]" = "1" |
| 140 | |
| 141 | # Disable CLKREQ#, since onboard LAN is always present |
| 142 | register "PcieRpClkReqSupport[5]" = "0" |
| 143 | register "PcieRpAdvancedErrorReporting[5]" = "1" |
| 144 | register "PcieRpLtrEnable[5]" = "1" |
| 145 | register "PcieRpClkSrcNumber[5]" = "1" |
| 146 | end |
| 147 | device pci 1c.6 on # PCI Express Port 7 - PCIE slot |
| 148 | register "PcieRpEnable[6]" = "1" |
| 149 | register "PcieRpClkReqSupport[6]" = "1" |
| 150 | register "PcieRpClkReqNumber[6]" = "3" |
| 151 | register "PcieRpAdvancedErrorReporting[6]" = "1" |
| 152 | register "PcieRpLtrEnable[6]" = "1" |
| 153 | register "PcieRpClkSrcNumber[6]" = "3" |
| 154 | register "PcieRpHotPlug[6]" = "1" |
| 155 | end |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 156 | device pci 1c.7 off end # PCI Express Port 8 |
| 157 | device pci 1d.0 off end # PCI Express Port 9 |
| 158 | device pci 1d.1 off end # PCI Express Port 10 |
| 159 | device pci 1d.2 off end # PCI Express Port 11 |
| 160 | device pci 1d.3 off end # PCI Express Port 12 |
| 161 | device pci 1e.0 off end # UART #0 |
| 162 | device pci 1e.1 off end # UART #1 |
| 163 | device pci 1e.2 off end # GSPI #0 |
| 164 | device pci 1e.3 off end # GSPI #1 |
| 165 | device pci 1e.4 off end # eMMC |
| 166 | device pci 1e.5 off end # SDIO |
Felix Singer | 5291952 | 2020-07-29 21:44:36 +0200 | [diff] [blame] | 167 | device pci 1e.6 off end # SDCard |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 168 | device pci 1f.0 on # LPC bridge |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 169 | subsystemid 0x1849 0x1a43 |
Maxim Polyakov | 66d875a | 2019-09-12 17:27:10 +0300 | [diff] [blame] | 170 | |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 171 | # Set @0x280-0x2ff I/O Range for SuperIO HWM |
| 172 | register "gen1_dec" = "0x007c0281" |
| 173 | |
| 174 | # Set LPC Serial IRQ mode |
| 175 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 176 | |
Maxim Polyakov | c4f77d9 | 2019-10-27 15:07:00 +0300 | [diff] [blame] | 177 | chip superio/common |
| 178 | device pnp 2e.0 on # passes SIO base addr to SSDT gen |
| 179 | |
| 180 | chip superio/nuvoton/nct6791d |
| 181 | device pnp 2e.1 on |
| 182 | # Global Control Registers |
| 183 | # Device IRQ Polarity |
| 184 | irq 0x13 = 0x00 |
| 185 | irq 0x14 = 0x00 |
| 186 | # Global Option |
| 187 | irq 0x24 = 0xfb |
| 188 | irq 0x27 = 0x10 |
| 189 | # Multi Function |
| 190 | irq 0x1a = 0xb0 |
| 191 | irq 0x1b = 0xe6 |
| 192 | irq 0x2a = 0x04 |
| 193 | irq 0x2c = 0x40 |
| 194 | irq 0x2d = 0x03 |
| 195 | |
| 196 | # Parallel Port |
| 197 | io 0x60 = 0x0378 |
| 198 | irq 0x70 = 7 |
| 199 | drq 0x74 = 4 # No DMA |
| 200 | irq 0xf0 = 0x3c # Printer mode |
| 201 | end |
| 202 | device pnp 2e.2 on # UART A |
| 203 | io 0x60 = 0x03f8 |
| 204 | irq 0x70 = 4 |
| 205 | end |
| 206 | device pnp 2e.3 on # IR |
| 207 | io 0x60 = 0x02f8 |
| 208 | irq 0x70 = 3 |
| 209 | end |
| 210 | device pnp 2e.5 on # PS/2 KBC |
| 211 | io 0x60 = 0x0060 |
| 212 | io 0x62 = 0x0064 |
| 213 | irq 0x70 = 1 # Keyboard |
| 214 | irq 0x72 = 12 # Mouse |
| 215 | end |
| 216 | device pnp 2e.6 off end # CIR |
| 217 | device pnp 2e.7 on # GPIO6 |
| 218 | irq 0xf6 = 0xff |
| 219 | irq 0xf7 = 0xff |
| 220 | irq 0xf8 = 0xff |
| 221 | end |
| 222 | device pnp 2e.107 on # GPIO7 |
| 223 | irq 0xe0 = 0x7f |
| 224 | irq 0xe1 = 0x0d |
| 225 | end |
| 226 | device pnp 2e.207 on # GPIO8 |
| 227 | irq 0xe6 = 0xff |
| 228 | irq 0xe7 = 0xff |
| 229 | irq 0xed = 0xff |
| 230 | end |
| 231 | device pnp 2e.8 off end # WDT |
| 232 | device pnp 2e.108 on end # GPIO0 |
| 233 | device pnp 2e.308 off end # GPIO base |
| 234 | device pnp 2e.408 off end # WDTMEM |
| 235 | device pnp 2e.708 on end # GPIO1 |
| 236 | device pnp 2e.9 on end # GPIO2 |
| 237 | device pnp 2e.109 on # GPIO3 |
| 238 | irq 0xe4 = 0x7b |
| 239 | irq 0xe5 = 0x02 |
| 240 | irq 0xea = 0x04 |
| 241 | end |
| 242 | device pnp 2e.209 on # GPIO4 |
| 243 | irq 0xf0 = 0x7f |
| 244 | irq 0xf1 = 0x80 |
| 245 | end |
| 246 | device pnp 2e.309 on # GPIO5 |
| 247 | irq 0xf4 = 0xdf |
| 248 | irq 0xf5 = 0xd5 |
| 249 | end |
| 250 | device pnp 2e.a on |
| 251 | # Power RAM in S3 and let the PCH |
| 252 | # handle power failure actions |
| 253 | irq 0xe4 = 0x70 |
| 254 | # Set HWM reset source to LRESET# |
| 255 | irq 0xe7 = 0x01 |
| 256 | end # ACPI |
| 257 | device pnp 2e.b on # HWM, LED |
| 258 | io 0x60 = 0x0290 |
| 259 | io 0x62 = 0 |
| 260 | irq 0x70 = 0 |
| 261 | end |
| 262 | device pnp 2e.d off end # BCLK, WDT2, WDT_MEM |
| 263 | device pnp 2e.e off end # CIR wake-up |
| 264 | device pnp 2e.f off end # GPIO PP/OD |
| 265 | device pnp 2e.14 off end # SVID, Port 80 UART |
| 266 | device pnp 2e.16 off end # DS5 |
| 267 | device pnp 2e.116 off end # DS3 |
| 268 | device pnp 2e.316 on end # PCHDSW |
| 269 | device pnp 2e.416 off end # DSWWOPT |
| 270 | device pnp 2e.516 on end # DS3OPT |
| 271 | device pnp 2e.616 on end # DSDSS |
| 272 | device pnp 2e.716 off end # DSPU |
| 273 | end # chip superio/nuvoton/nct6791d |
| 274 | |
| 275 | end # device pnp 2e.0 |
| 276 | end # chip superio/common |
| 277 | |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 278 | chip drivers/pc80/tpm |
| 279 | device pnp 4e.0 on end # TPM module |
| 280 | end |
| 281 | end # LPC Interface |
| 282 | device pci 1f.1 on end # P2SB |
| 283 | device pci 1f.2 on end # Power Management Controller |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 284 | device pci 1f.3 on # Intel HDA |
| 285 | register "PchHdaVcType" = "Vc1" |
Angel Pons | e18cdf4 | 2020-07-26 20:54:09 +0200 | [diff] [blame] | 286 | end |
Maxim Polyakov | 1217af5 | 2019-02-25 11:06:19 +0300 | [diff] [blame] | 287 | device pci 1f.4 on end # SMBus |
| 288 | device pci 1f.5 on end # PCH SPI |
| 289 | device pci 1f.6 off end # GbE |
| 290 | end |
| 291 | end |